Publications associées à Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

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Synthesis and optimization of high-level stream programs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

In this paper we address the problem of translating high-level stream programs, such as those written in MPEG's RVC-CAL dataflow language, into implementations in programmable hardware. Our focus is on two aspects: sufficient language coverage to make synt ...

2013

Synthesis And Optimization Of High-Level Stream Programs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

Ieee2013

Power Consumption of Logic Circuits in Ambipolar Carbon Nanotube Technology

Giovanni De Micheli, Mohamed Haykel Ben Jamaa

Ambipolar devices have been reported in many technologies, including carbon nanotube field effect transistors (CNTFETs). The ambipolarity can be in-field controlled with a second gate, enabling the design of generalized logic gates with a high expressive p ...

2010

Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis

Giovanni De Micheli, Mohamed Haykel Ben Jamaa

This paper exploits the unique in-ﬁeld controllability of the device polarity of ambipolar carbon nanotube ﬁeld effect transistors (CNTFETs) to design a technology library with higher expressive power than conventional CMOS libraries. Based on generalized ...

2009

Arithmetic Optimization for Custom Instruction Set Synthesis

Paolo Ienne, Philip Brisk, Ajay Kumar Verma, Yi Zhu

One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arithmetic level. Arithmetic hardware, in many cases, can be partitioned into networks of f ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Challenges in Automatic Optimization of Arithmetic Circuits

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, especially for arithmetic circuits. In many cases, the outcome of even the most adv ...

Ieee Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, Ca 90720-1264 Usa2009

Approximate BDD Minimization by Weighted A*

Reduced ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synthesis. The size of BDDs depends on a chosen variable ordering, i.e. the size may ...

Institute of Electrical and Electronics Engineers2009

On the Complexity of the Port Assignment Problem for Binary Commutative Operators in High-Level Synthesis

Paolo Ienne, Philip Brisk

The present formulation of the port assignment problem for binary commutative operators tries to minimize the number of wires connected to both the left and right inputs of the operator; intuitively, this minimizes the total number of inputs connected to b ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

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Synthesis and optimization of high-level stream programs

Synthesis And Optimization Of High-Level Stream Programs

Closing the Gap between FPGA and ASIC

Power Consumption of Logic Circuits in Ambipolar Carbon Nanotube Technology

Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis

Arithmetic Optimization for Custom Instruction Set Synthesis

Challenges in Automatic Optimization of Arithmetic Circuits

Approximate BDD Minimization by Weighted A*

On the Complexity of the Port Assignment Problem for Binary Commutative Operators in High-Level Synthesis

Low Overhead DFT Using CDFG by Modifying Controller

Closing the Gap between FPGA and ASIC

Synthesis And Optimization Of High-Level Stream Programs

Synthesis and optimization of high-level stream programs

Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis

Low Overhead DFT Using CDFG by Modifying Controller

Arithmetic Optimization for Custom Instruction Set Synthesis

Power Consumption of Logic Circuits in Ambipolar Carbon Nanotube Technology

Challenges in Automatic Optimization of Arithmetic Circuits

Approximate BDD Minimization by Weighted A*

On the Complexity of the Port Assignment Problem for Binary Commutative Operators in High-Level Synthesis