Closing the Gap between FPGA and ASIC

Despite many advantages of Field-Programmable Gate Arrays (FPGAs), they fail to take over the IC design market from Application-Specific Integrated Circuits (ASICs) for high-volume and even medium-volume applications, as FPGAs come with significant cost in area, delay, and power consumption. There are two main reasons that FPGAs have huge efficiency gap with ASICs: (1) FPGAs are extremely flexible as they have fully programmable soft-logic blocks and routing networks, and (2) FPGAs have hard-logic blocks that are only usable by a subset of applications. In other words, current FPGAs have a heterogeneous structure comprised of the flexible soft-logic and the efficient hard-logic blocks that suffer from inefficiency and inflexibility, respectively. The inefficiency of the soft-logic is a challenge for any application that is mapped to FPGAs, and lack of flexibility in the hard-logic results in a waste of resources when an application cannot use the hard-logic. In this thesis, we approach the inefficiency problem of FPGAs by bridging the efficiency/flexibility gap of the hard- and soft-logic. The main goal of this thesis is to compromise on efficiency of the hard-logic for flexibility, on the one hand, and to compromise on flexibility of the soft-logic for efficiency, on the other hand. In other words, this thesis deals with two issues: (1) adding more generality to the hard-logic of FPGAs, and (2) improving the soft-logic by adapting it to the generic requirements of applications. In the first part of the thesis, we introduce new techniques that expand the functionality of FPGAs hard-logic. The hard-logic includes the dedicated resources that are tightly coupled with the soft-logic –i.e., adder circuitry and carry chains –as well as the stand-alone ones –i.e., DSP blocks. These specialized resources are intended to accelerate critical arithmetic operations that appear in the pre-synthesis representation of applications; we introduce mapping and architectural solutions, which enable both types of the hard-logic to support additional arithmetic operations. We first present a mapping technique that extends the application of FPGAs carry chains for carry-save arithmetic, and then to increase the generality of the hard-logic, we introduce novel architectures; using these architectures, more applications can take advantage of FPGAs hard-logic. In the second part of the thesis, we improve the efficiency of FPGAs soft-logic by exploiting the circuit patterns that emerge after logic synthesis, i.e., connection and logic patterns. Using these patterns, we design new soft-logic blocks that have less flexibility, but more efficiency than current ones. In this part, we first introduce logic chains, fixed connections that are integrated between the soft-logic blocks of FPGAs and are well-suited for long chains of logic that appear post-synthesis. Logic chains provide fast and low cost connectivity, increase the bandwidth of the logic blocks without changing their interface with the routing network, and improve the logic density of soft-logic blocks. In addition to logic chains and as a complementary contribution, we present a non-LUT soft-logic block that comprises simple and pre-connected cells. The structure of this logic block is inspired from the logic patterns that appear post-synthesis. This block has a complexity that is only linear in the number of inputs, it sports the potential for multiple independent outputs, and the delay is only logarithmic in the number of inputs. Although this new block is less flexible than a LUT, we show (1) that effective mapping algorithms exist, (2) that, due to their simplicity, poor utilization is less of an issue than with LUTs, and (3) that a few LUTs can still be used in extreme unfortunate cases. In summary, to bridge the gap between FPGAs and ASICs, we approach the problem from two complementary directions, which balance flexibility and efficiency of the logic blocks of FPGAs. However, we were able to explore a few design points in this thesis, and future work could focus on further exploration of the design space.

In-IC Strategies for 3D Devices in Bulk Silicon

Matthieu Bopp

The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law during more than 40 years. Today the traditional scaling has reached limits when physical phenomena inherent to the nanoscale generate as many challenges and issues as the gain in performance compared to previous device generation. This work proposes another alternative to overcome the difficulty of traditional scaling and still continue to increase the integration density and with improved device performances: the vertical stacking of devices or the completion of the planar integration with an in-volume, vertical integration of multiple channels and other structures. In contrast with many other works, we investigated stacking of channel on bulk silicon substrates which will avoid the higher costs of engineered substrates like SOI. This thesis reports on the development of strategies to fabricate advanced multilevel 3D structures in bulk silicon, and their integration as stacked transistor channels. We propose some credible alternatives for the design, fabrication and characterization of a Field Effect Transistor exploiting vertically stacked channels. We investigate two main technologies: (i) silicon transformation during a high temperature annealing in hydrogen ambient, and, (ii) profile engineered trenches. We propose several design and process optimization to be able to fabricate stacked silicon structures (membranes, nanowires, Fins) that could be used as suspended transistor channels. Two original fabrication processes are presented, enabling the manufacturing of bulk silicon transistors with a matrix of stacked channels. We successfully validate the fabrication process of two level suspended Fin channel transistor. Double-stacks of nanowires stacks (promoting a new concept of stacking the stacks) are also demonstrated morphologically. Some of the fabricated structures are electrically characterized, demonstrating basic functionally of a MOSFET but also some difficult control of parasitic transistor effect. We have tried to eliminate such effects by a special design of the source and drain pads in a second integration process. The transfer, Id-Vg, and output, Id-Vd, characteristics of fabricated devices always show a transistor behavior and the extracted mobility values for n-type transistors tend to confirm that the conduction in the suspended channels dominates over the sidewall or bottom parasitic transistor. However, the presence of a parasitic transistor remains important and its elimination needs further efforts. The demonstrated 3D silicon structures in this work show the possibility to sculpture and integrate stacked channels in bulk silicon for making MOSFETs with multiple suspended channels, potentially with independently control of these channels. The morphological work carried out can also find novel applications in other silicon applications areas, like photonics, micro fluidics and Micro-Electro-Mechanical-Systems.

EPFL2011

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Nithin George

Field Programmable Gate Arrays (FPGAs) have the unique ability to be configured into application-specific architectures that are well suited to specific computing problems. This enables them to achieve performances and energy efficiencies that outclass other processor-based architectures, such as Chip Multiprocessors (CMPs), Graphic Processing Units (GPUs) and Digital Signal Processors (DSPs). Despite this, FPGAs are yet to gain widespread adoption, especially among application and software developers, because of their laborious application development process that requires hardware design expertise. In some application areas, domain-specific hardware synthesis tools alleviate this problem by using a Domain-Specific Language (DSL) to hide the low-level hardware details and also improve productivity of the developer. Additionally, these tools leverage domain knowledge to perform optimizations and produce high-quality hardware designs. While this approach holds great promise, the significant effort and cost of developing such domain-specific tools make it unaffordable in many application areas. In this thesis, we develop techniques to reduce the effort and cost of developing domain-specific hardware synthesis tools. To demonstrate our approach, we develop a toolchain to generate complete hardware systems from high-level functional specifications written in a DSL. Firstly, our approach uses language embedding and type-directed staging to develop a DSL and compiler in a cost-effective manner. To further reduce effort, we develop this compiler by composing reusable optimization modules, and integrate it with existing hardware synthesis tools. However, most synthesis tools require users to have hardware design knowledge to produce high-quality results. Therefore, secondly, to facilitate people without hardware design skills to develop domain-specific tools, we develop a methodology to generate high-quality hardware designs from well known computational patterns, such as map, zipWith, reduce and foreach; computational patterns are algorithmic methods that capture the nature of computation and communication and can be easily understood and used without expert knowledge. In our approach, we decompose the DSL specifications into constituent computational patterns and exploit the properties of these patterns, such as degree of parallelism, interdependence between operations and data-access characteristics, to generate high-quality hardware modules to implement them, and compose them into a complete system design. Lastly, we extended our methodology to automatically parallelize computations across multiple hardware modules to benefit from the spatial parallelism of the FPGA as well as overcome performance problems caused by non-sequential data access patterns and long access latency to external memory. To achieve this, we utilize the data-access properties of the computational patterns to automatically identify synchronization requirements and generate such multi-module designs from the same high-level functional specifications. Driven by power and performance constraints, today the world is turning to reconfigurable technology (i.e., FPGAs) to meet the computational needs of tomorrow. In this light, this work addresses the cardinal problem of making tomorrow's computing infrastructure programmable to application developers.

EPFL2016

Data Structures and Algorithms for Logic Synthesis in Advanced Technologies

Eleonora Testa

Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolved dramatically, facing many technological changes. Consequently, EDA and logic synthesis have adapted to accurately design the new generation of digital systems. In the present day, logic synthesis is an important area of research for two main reasons: (i) Diverse ways of computation, alternative to CMOS, have been presented in the last years. Post-silicon technologies have been shown to be feasible and may provide us with better electronic devices. Similarly, novel areas of applications are emerging, ranging from deep learning to cryptography applications. (ii) The current computing and storage means make it possible to solve exactly problems that were only approximated before. Moreover, new reasoning engines, covering from deep learning to new SAT-solvers, can be used as a mean of computation, thus possibly unlocking novel optimization opportunities. The objective of this thesis is to advance state-of-the-art logic synthesis and present a variety of novel data structures and algorithms, addressing diverse types of applications in modern logic synthesis flows, considering standard CMOS design as well as emerging technology and cryptography. Motivated by the many emerging technologies that implement majority gates, we first focus on majority-based logic synthesis. We present algorithms over the recently introduced majority-inverter graphs. First, a size optimization flow based on Boolean transformations is proposed. Then, we demonstrate how technology-dependent logic synthesis is an essential step for the abstraction of majority-based emerging technologies and, more important, their technological constraints. Moreover, we advance theoretical results on majority logic. In particular, we mainly focus on the problem of ''how best can the n-argument majority function (majority-n) be realized with a network of 3-input majority gates?''. For this purpose, we present general upper bounds and decompositions, together with optimum results for majority-5 and -7 and best-known results for the majority-9. In the second part, we shift into more pragmatic results and show practical aspects of logic synthesis, designed to be successful in modern logic synthesis flows. We focus on XOR-based logic synthesis. Motivated by the novel computing capabilities, we propose an optimization flow based on the Boolean difference for area optimization of standard CMOS technologies. Finally, we establish a novel application of logic synthesis to cryptography. It has been demonstrated that the number of AND gates in a xor-and graph (XAG) correlates with the degree of vulnerability (security) of cryptography benchmarks and plays an important role for high-level cryptography protocols. We thus introduce a complete and automatic synthesis flow which consists of the main transformations of logic synthesis but aims instead at minimization of the number of AND gates over XAGs, obtaining significant results over cryptography benchmarks. We argue that given the progress and novel opportunities of technology, logic synthesis has to be revisited to consider the plurality of primitives and novel engines that can be of interest, and, consequently, the corresponding objective functions and optimisation problems.

EPFL2020