Publications associées à ShiDianNao: shifting vision processing closer to the sensor

This column introduces seven invited position papers about the challenges and opportunities in near-data processing. "Near-Memory Data Services" by Babak Falsafi, "Automata Processing: The Memory Is the Processor!" by Mircea Stan, Kevin Skadron, "Overcomin ...

Institute of Electrical and Electronics Engineers2016

A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Pascal Andreas Meinerzhagen

Gain cell embedded DRAM (GC-eDRAM) is a high-density alternative to SRAM for ultra-low-power systems. However, due to its dynamic nature, GC-eDRAM requires power-hungry refresh cycles to ensure data retention. Traditional design approaches dictate configur ...

Ieee2016

Challenges of Memory Management on Modern NUMA Systems

Baptiste Joseph Eustache Lepers, Mohammad Dashti Rahmat Abadi

The latency of memory access times is hence non-uniform, because it depends on where the request originates and where it is destined to go. Such systems are referred to as nonuniform memory access (or NUMA). Current x86 NUMA systems are cache coherent (cal ...

Assoc Computing Machinery2015

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Pascal Andreas Meinerzhagen, Georgios Karakonstantis

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst- ...

2015

Scaling the Memory Power Wall with DRAM-Aware Data Management

Anastasia Ailamaki, Raja Appuswamy, Matthaios Alexandros Olma

Improving the energy efficiency of database systems has emerged as an important topic of research over the past few years. While significant attention has been paid to optimizing the power consumption of tradition disk-based databases, little attention has ...

ACM2015

BuMP: Bulk Memory Access Prediction and Streaming

Babak Falsafi, Boris Robert Grot, Stavros Volos, Javier Picorel Obando

With the end of Dennard scaling, server power has emerged as the limiting factor in the quest for more capable datacenters. Without the benefit of supply voltage scaling, it is essential to lower the energy per operation to improve server efficiency. As th ...

2014

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Pascal Andreas Meinerzhagen

Gain cells have recently been shown to be a viable alternative to static random access memory in low-power applications due to their low leakage currents and high density. The primary component of power consumption in these arrays is the dynamic power cons ...

Institute of Electrical and Electronics Engineers2014

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

Giovanni De Micheli, Luca Benini, Ciprian Seiculescu

Achieving the main memory (DRAM) required bandwidth at ac- ceptable power levels for current and future applications is a ma- jor challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM mem- ories ...

2012

A DRAM Centric NoC Architecture and Topology Design Approach

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Most communication traffic in today’s System on Chips (SoC) is DRAM centric. The NoC should be designed to efficiently handle the many-to-one communication pattern, funneling to and from the DRAM controller. In this paper, we motivate the use of a separate ...

Ieee Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, Ca 90720-1264 Usa2011

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ShiDianNao: shifting vision processing closer to the sensor

Near-Memory Data Services

A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design

Challenges of Memory Management on Modern NUMA Systems

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories

Scaling the Memory Power Wall with DRAM-Aware Data Management

BuMP: Bulk Memory Access Prediction and Streaming

Single event upset mitigation in low power SRAM design

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

A DRAM Centric NoC Architecture and Topology Design Approach

Graph Chatbot

Chattez avec Graph Search

Scaling the Memory Power Wall with DRAM-Aware Data Management

Challenges of Memory Management on Modern NUMA Systems

Near-Memory Data Services

Single event upset mitigation in low power SRAM design

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories

BuMP: Bulk Memory Access Prediction and Streaming

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

A DRAM Centric NoC Architecture and Topology Design Approach