Etude formelle pour la synthèse de convertisseurs multiniveaux asymétriques

The multilevel converters allow generating a voltage waveform whose magnitude and quality are higher than those of conventional converters. They are devoted to medium and high-voltage, high-switching-frequency applications. Among the series connected cell inverters, the symmetrical multilevel inverters are made of identical cells, which topology is generally the H-bridge inverter. This dissertation deals with asymmetrical multilevel converters, which combine high-voltage cells — made of low conduction loss switches — with low-voltage cells — made of low switching loss switches. The different cells play different roles. The goal is to design a converter that has both better energetic efficiency and higher resolution with the same number of cells. This dissertation develops a set of tools that allows synthesizing an asymmetrical multilevel converter. It develops the cell combination rules, which allow defining several cell association classes. The inverter step uniformity condition determines the finesse that can be reached. The optimized modulation condition allows to reduce the highvoltage cell switching frequency without changing the low-voltage cell switching frequency. This property is essential to derive benefit from combining switches of different characteristics. The power balance condition determine how to control the power sharing between the cells. These association classes are different for the single-phase converters and the three-phase converters — without neutral wire. They allow to select a configuration suitable for a given application. Furthermore, several ways that allow improving the inverter resolution are investigated. The modulation is essential to associate a high-quality signal (which will really be delivered to the load by means of the inverter levels) to the reference signal (which should ideally be applied to the load). The modulator evaluation methods are assessed. An approach—based on the modulated signal decomposition in elementary frames—is proposed. The main modulator drawbacks are highlighted. A modulator—which arrange the frames in order—allows to reduce the modulated signal distortion and number of transitions. The specific control methods that allow to minimize the inverter number of switchings are developed. The active power cell supply implies several conversion stages, which decrease the converter energetic efficiency. Some solutions that allow to reduce these losses are proposed. Finally, this dissertation attempts to determine, which are the more interesting solutions, depending on the application.

Symmetrical multilevel converters with two quadrant DC-DC feeding

In the technology sector of power electronics and control, the multilevel converter technology is still a rather new research area, but the application possibilities in the field of power drives and energy will demand more solutions with this promising technology. In the future, more converter systems will be realized with the multilevel topology. Up to now, multilevel converters have only been used in very particular applications, mainly due to the high costs and complexity of the multilevel converter system. The high costs are due to the fact that the latest technology on semiconductors, magnetic material for inductor and transformer cores and control system technology had to be used. But nowadays new developments in the fields of power semiconductors such as the IGBT, IGCT and perhaps in the future SiC switches as well as improvements of the performance of magnetic cores used in medium frequency transformers will favor the multilevel converters for many other application fields. It can be noted that the industrial trend is moving away from heavy and bulky passive components towards power converter systems using more and more semiconductor elements controlled by powerful processor systems integrating intelligent multi-task control algorithms. The presented work is a contribution to the large field of multilevel converters. It shows a certain kind of multilevel converter in a single phase and a three-phase configuration, called the series-connected four-quadrant converters (SCFQ). The two specialties of the presented converter type are a) that all the multilevel converter steps are fed by an identical DC voltage and b) that every multilevel converter step is realized with an individual AC-DC converter or four-quadrant converter. This type of multilevel converter is called multilevel converter with symmetrical feeding. In this work, a general theoretical development has been done for the use of this multilevel converter type. A special type of DC-DC converter is presented, in order to feed the individual four-quadrant converters of the multilevel converter with a constant DC voltage. All the developments and methods used are based on mathematical expressions. Various simulations using the latest software simulation tools are accomplished and are used to study different cases. The feasibility of the developments is underlined with a series of experimental results with all types of the used converters, which have been realized in the framework of this thesis. The main application for the multilevel converter presented in this work is the frontend power converter in locomotives. Instead of using a heavy low-frequency transformer to reduce the high-voltage from the catenary to a supportable voltage for the semiconductors, a multilevel converter concept is used. The multilevel converter is directly coupled to the catenary. There are many advantages compared to the existing solutions. In the same context, a novel solution of a multilevel converter has been developed for a locomotive usable on different power lines. The converter allows not only the operation on the high AC voltage power line (15kV), but also can be coupled to a medium-voltage DC power line (3kV). Three different configuration types of the locomotive converter have been developed and tested in a complex simulation environment. Besides the locomotive application, there are many more interesting applications for the symmetrical multilevel converter, e.g. in the fields of energy transmission (FACTS, static VAR compensators, electronic high-voltage transformers, etc.) and industrial drives. But certainly in the future with the availability of cheap semiconductors adapted to the needs of the multilevel converter, even more applications in lower power fields will be realized.

EPFL2000

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

Sergio Pesenti

In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established and highly automated design flow allows one to benefit from the constant progress in CMOS technologies. Moreover, digital circuits offer robust and programmable signal processing means and need no external components. Hence, the trend in consumer electronics is to further reduce the part of analog signal processing in the receiver chain of wireless transceivers. Consequently, analog-to-digital converters with higher resolutions and bandwidths are constantly required. The ultimate goal is the direct digitization of radio frequency signals, where the conversion would be performed immediately after the front-end amplifier. ΔΣ-modulation-based converters have proved to be the most suitable to achieve the required performance. Switched-capacitor implementations have been widely used over the last two decades. However, recent publications and books have shown that continuous-time architectures can achieve the same performance with lower power consumption. Most designs found throughout the literature use a single- or few-bit internal quantizer with a high-order modulation. As a result, in order to achieve the resolutions and bandwidths required today, the sampling frequency must exceed 100MHz. This approach leads to non-negligible power consumption in the clock generation. Moreover, the presence of such fast squared signals is not suitable for a system-on-chip comprising radio frequency receivers. In this thesis we propose a low-power strategy relying on a large number of internal levels rather than on a high sampling frequency or modulation order. Besides, a hybrid continuous-discrete-time approach is used to take advantage of the accuracy of switched-capacitor circuits and the low power consumption of continuous-time implementation. The sensitivity to clock jitter brought about by the continuous-time stage is reduced by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer under low-voltage supply. Finally, the strategy is applied to a design example addressing typical specifications for a Bluetooth receiver with direct conversion.

EPFL2007

Convertisseurs multiniveaux asymétriques alimentés par transformateurs multi-secondaires basse-fréquence

Joseph Song Manguelle

In the last years, static power converters have become widely used in various applications. They can be found in domestic applications, railways, urban and ship transport, and even in several industrial systems. Some of these applications require a high or medium voltage power supply that is easily adjustable while providing good spectral performances. To overcome the maximum blocking voltage limits of the main power switches, multilevel techniques and other new power conversion topologies have been developed. They are series/parallel associations of existing power semiconductors, and allow generating an output voltage with many levels. The number of power semiconductors needed in these topologies increases as the number of levels increases. The power converter circuit becomes more complex and its reliability decreases. This thesis focuses on three-phase multilevel converters based on a series connection of single phase inverters (partial cells) in each phase. It's shown that, feeding partial cells with unequal DC-voltages (asymmetric feeding), increases the number of levels of the generated output voltage without any supplemental complexity to the existing topology. Voltage resolution is increased through interpolating the generated output voltage phasor (three phase voltage in α-β frame). This is achieved by seeking the non redundant switching states of the power switches. The resultant converter can generate a very high resolution voltage phasor up to the possible maximum resolution. This approach is generalized for any number of partial cells. Each partial cell is fed through a three-phase diode rectifier, fed itself through the windings of a multi-secondary low frequency power transformer. From analytical expressions in continuous and discontinuous current conix duction modes, it is shown that, from a supply network point of view, a symmetrical multilevel converter has a smaller total harmonic distortion than an asymmetrical multilevel converter with the same number of partial cells per phase. An asymmetrical multilevel converter is not more interesting than a classical three-phase converter, but its total harmonic distortion is compatible to the recommended IEEE std 519-1992. It is also shown that the advantages of an asymmetric multilevel converter from a load point of view (generation of a high resolution voltage phasor, possibility to choose the number of redundant switching states, reduction of the number of power semiconductors for the same voltage resolution, flexibility for the DC-voltage feeding choice) and the advantages of a symmetrical multilevel converter from a supply network point of view (smaller total harmonic distorsion) can be combined. Simulation results and the experimental test setup showed the reliability of the suggested approach.

EPFL2004