Methodology for the digital calibration of analog circuits and systems
Graph Chatbot
Chattez avec Graph Search
Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.
AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.
This thesis describes a novel digital background calibration scheme for pipelined ADCs with nonlinear interstage gain. Errors caused by the nonlinear gains are corrected in real-time by adaptively post-processing the digital stage outputs. The goal of this ...
An event-driven tracking analog to digital converter (ADC) architecture is proposed. The proposed architecture has less sensitivity to amplifier and DAC non-linearity, reduces the swing and dynamic common-mode range requirement of the operational transcond ...
In a nonideal PLL circuit, leakage of the reference signal into the control line produces spurious tones. When the distorted PLL signal is used in an analog-to-digital converter (ADC), it injects the spurious tones into the sampled data. These distortions ...
The potentials of subthreshold metal-oxide-semiconductor (MOS) solid-state devices for implementing widely adjustable performance integrated circuits with very low power consumption have been investigated. The main concentration of this work is developing ...
A topology for the calibration of DAC errors in multi-bit sigma delta modulators is presented. The proposed technique enables the calibration to proceed in the background. In this technique, two DACs are used in a time-interleaved fashion. One DAC is calib ...
In a semiconductor market dominated by portable consumer applications, embedded flash memory technology has experienced a rapid diffusion. It is now considered the preferred solid-state memory solution for its non-volatile characteristics, high read and wr ...
A technique for the calibration of DAC (digital to analog converter) mismatch errors in multi-bit Sigma Delta modulators (SDM) is presented. It consists of two parts: the first is a measurement technique to obtain the relative mismatch of each feedback DAC ...
In the past decades, two recording tools have established themselves as the working horses in the field of electrophysiological cell research: the microelectrode array (MEA) and the optical fluorescence imaging. The former is a grid of miniature electrodes ...
An 8b 1.2GS/s single-channel SAR converter is implemented in 32nm CMOS, achieving 39.3dB SNDR and a FOM of 34fJ/conversion-step. High-speed operation is achieved by converting each sample with two alternating comparators clocked asynchronously and a redund ...
A surface potential-based model for embedded flash memory cells has been developed with the purpose of providing a comprehensive physical understanding of the device operation suitable for performance optimization in memory circuit design. The device equat ...