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Self-Calibrating Networks-On-Chip

Publications associées (37)

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Offset Compensation Based on Distributed Hall Cell Architecture

Pierre-André Farine, Pavel Kejik, Pierre-François Thibault Bourdelle

A new offset reduction strategy for CMOS Hall devices is proposed. The novelty is to fragment the Hall device into multiple Hall blocks, distributed over the silicon area and easy to interconnect. The suitable number of Hall blocks and the bias current lev ...

Ieee-Inst Electrical Electronics Engineers Inc2013

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An integrated chip for DNA hybridization detection was realized in a standard CMOS process: it hosts 80 biosensors subdivided in 2 channels, as well as D/A and A/D converters for electrical stimulation and readout. A microfluidic system, bonded on the surf ...

Elsevier2012

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We propose a technique to localize computation in Instruction Set Extensions (ISEs) that are clocked at very high speed with respect to the processor. In order to save power, data to and from Custom Instruction Units (CIUs) is synchronized via an optical s ...

2012

Parallel Programmable Asynchronous Neighborhood Mechanism for Kohonen SOM Implemented in CMOS Technology

Rafal Tomasz Dlugosz

We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. T ...

Institute of Electrical and Electronics Engineers2011

A fully integrated IQ-receiver for NMR microscopy

Giovanni Boero, Jens Anders, Paul Sangiorgio

We present a fully integrated CMOS receiver for micro-magnetic resonance imaging together with a custom-made micro-gradient system. The receiver is designed for an operating frequency of 300 MHz. The chip consists of an on-chip detection coil and tuning ca ...

2011

Single-Photon Techniques for Standard CMOS Digital ICs

Claudio Favi

The advent of single-photon detectors known as Single-Photon Avalanche Diodes in standard CMOS technology opened the way to new perspectives in integrating these ultra sensitive light sensors with digital logic. Light has some interesting properties that a ...

EPFL2011

A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the transmission protocol in NoCs, as it offers high throughput and low latency. To mat ...

2010

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Random telegraph signal (RTS) behavior is reported and characterized in the dark count rate of single-photon avalanche Diodes (SPADs). The RTS is observed in a SPAD fabricated in 0.8-mu m CMOS technology and in four proton-irradiated SPADs designed and fab ...

Institute of Electrical and Electronics Engineers2010

The invention of the integrated circuit and the manufacturing progress as well as continuing progress in the manufacturing process are the fundamental engines for the implementation of all technologies that support today's information society. The vast maj ...

EPFL2009

Improving the power-delay performance in subthreshold source-coupled logic circuits

Seyed Armin Tajalli, Yusuf Leblebici

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved pow ...

Springer2009