Intelligent RF System for Ultra Low Power Spectrum Sensing with Machine Learning

The crowdedness of the RF spectrum constitutes problems in communication, however it also accommodates large amount of useful information. This information can be used to determine existing signals and operating contexts. However, spectrum condition varies profoundly and each condition possesses different processing challenges. Although an optimal power consumption is achievable for each given context, the literature lacks approaches for context-aware system adaptation and low-power hardware implementation.

This thesis focuses on defining a generic method to extract information from the spectrum with the optimal power consumption under varying operating conditions. To demonstrate the generic method, a Wi-Fi, Bluetooth, and microwave oven signal detection system is proposed. Prior work showed that analog pre-processing is more power efficient than digital in low precision. Hence, the proposed system consists of an integrated highly configurable analog feature extractor (AFE) followed by off-chip digital ML classifiers.

First, signal processing solutions are investigated and novel system level architectures are proposed. The proposed context-aware and intelligent duty-cycled (DC) operation schemes are detailed. I also discuss various power saving schemes. Second, modeling of aforementioned target signals and context scenarios are discussed. Sparse and medium-crowded spectra are considered in this work. Highly-crowded spectrum requires very high dynamic range, and is out of the scope of this work. Novel and patented low-power features are proposed.

A top-down design methodology was used in this work and design discussions start with system level design aspects. The proposed base-band analog signal processor utilizes complex valued processing and consists of a variable-gain amplifier, a 4-channel complex band-pass filter (CBPF) bank, transconductors (OTA), and AFE blocks.

The proposed sensing radio was designed and fabricated in GF 22FDX technology. A charge-based differential-pair non-linearity model is also developed for low-power analog circuit optimization. Measurement results showed excellent agreement with the analytic model even for deep sub-micron devices. Then, building block design details and characterization results are presented.

The AFE consumes only 5µW and the OTA consumes 7µW. The CBPF bank consumption ranges from 39µW to 138µW depending on the frequency setting. In sparse context setting, the system incorporates the VGA and a full-band AFE, and consumes 216µW, only 11% of which is consumed by the AFE. Power consumption of the overall system consisting of the VGA, the CBPF bank, and all the AFEs ranges from 353µW to 452µW in medium-crowded context. Reported power consumptions are from a 0.8V power supply in always-on operation. The proposed DC scheme reduces average power to 58µW for sparse and to the range from 96µW to 121µW for medium-crowded contexts with only 11µs worst case detection latency. The average power consumption c