Bringing NoCs to 65nm

Publications associées (30)

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Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Yusuf Leblebici

Thermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40nm CMOS node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations an ...

Elsevier Science Bv2017

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Hassan Ghasemzadeh Mohammadi

Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon ...

EPFL2016

Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design

Maria-Anna Chalkiadaki

The evolution and characteristics of the electronics is directly linked to the technological and societal progress. Today, there is a huge variety of electronic solutions offered, with the RF low-power systems, such as wireless sensor networks, wireless bo ...

EPFL2016

Sub-electron CIS noise analysis in 65 nm process

Christian Enz, Assim Boukhayma, Raffaele Capoccia

For a 4T pixel-based CMOS image sensors (CIS) readout chain, with column-level amplification and CDS, we show that the input-referred total noise in a standard 65 nm process can be reduced to 0.37 e-rms. Based on transient noise simulation using Eldo, the ...

2016

A Relative Imaging CMOS Image Sensor for High Dynamic Range and High Frame-Rate Machine Vision Imaging Applications

Alexandre Schmid, Yusuf Leblebici, Vladan Popovic, Nikola Katic, Radisav Cojbasic

This paper proposes an unconventional image acquisition scheme for machine vision applications, based on detecting ratios of illumination (pixel) intensities. Detecting relative ratios enables capturing the scene features and patterns almost independently ...

Institute of Electrical and Electronics Engineers2015

A Low Power On-Chip Class-E Power Amplifier For Remotely Powered Implantable Sensor Systems

Catherine Dehollain, Enver Gürhan Kilinç, Kerim Türe

This paper presents a low power fully integrated class-E power amplifier and its integration with remotely powered sensor system. The class-E power amplifier is suitable solution for low-power applications due to its high power efficiency. However, the req ...

Spie-Int Soc Optical Engineering2015

A 533pW NEP 31×31 pixel THz image sensor based on in-pixel demodulation

Christian Enz, Assim Boukhayma

A THz 31×31 pixel, 100 fps image sensor integrated in a 130 nm CMOS process is presented. Taking advantage of the possibility to modulate the active source that lights the scene, a significant improvement in sensitivity and NEP is achieved by shifting the ...

2014

Design and Implementation of CMOS Image Sensors for Biomedical Applications

Gözen Köklü

Since the first introduction of digital cameras, the camera market has been taking tremendous interest from many fields. This trend has even accelerated when the cost, size, and power consumption of such devices were reduced with the introduction of camera ...

EPFL2014

Low-power RF modeling of a 40nm CMOS technology using BSIM6

Christian Enz, Maria-Anna Chalkiadaki

The state-of-the-art scaled down CMOS processes have led to devices with extremely high Ft reaching several hundreds of GHz. This high F t can be traded with power consumption by moving the operating point towards weak inversion with Ft reaching tens of GH ...

2013

Effects of Process Variations on 3-D Global Clock Distribution Networks

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this ...

Assoc Computing Machinery2012

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