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Hiding Synchronization Delays in a GALS Processor Microarchitecture

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

Inter-actions parallel execution on GPU from high-level dataflow synthesis

Micro-architectural analysis of in-memory OLTP: Revisited

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis

Improving Main-memory Database System Performance through Cooperative Multitasking

LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching

Exploiting Compute Caches for Memory Bound Vector Operations

Low-Overhead Dynamic Instruction Mix Generation using Hybrid Basic Block Profiling

Characterization of the Impact of Hardware Islands on OLTP

Graph Chatbot

Chattez avec Graph Search

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

Improving Main-memory Database System Performance through Cooperative Multitasking

Exploiting Compute Caches for Memory Bound Vector Operations

Inter-actions parallel execution on GPU from high-level dataflow synthesis

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis

Micro-architectural analysis of in-memory OLTP: Revisited

LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching

Low-Overhead Dynamic Instruction Mix Generation using Hybrid Basic Block Profiling

Characterization of the Impact of Hardware Islands on OLTP