Publications associées à Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density

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An area and power optimization technique for CMOS bandgap voltage references

Seyed Armin Tajalli, Mohammad Chahardori

This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose ...

Springer US2010

Improving the power-delay performance in subthreshold source-coupled logic circuits

Seyed Armin Tajalli, Yusuf Leblebici

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved pow ...

Springer2009

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits

Seyed Armin Tajalli, Yusuf Leblebici

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2009

Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits

Seyed Armin Tajalli, Yusuf Leblebici

This article presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. A source follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18um ...

2009

Power Distribution Paths for 3-D IC

Giovanni De Micheli, Vasileios Pavlidis

Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (TSVs) in most of the manufacturing techniques for three-dimensional (3-D) cir ...

ACM Order Department, P.O. Box 64145, Baltimore, MD 21264 USA2009

A Novel Complex Gm-C IF Sub-Sampling Mixer

Christian Enz, Aravind Prasad Heragu Singaiyengar

In this paper, a novel circuit referred to as complex Gm-C sampler that can be used for sub-sampling IF signals is presented. The circuit employs a conventional cross-coupled Gm-C filter structure with a built-in sampler to combine th ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Pico-Watt Source-Coupled Logic Circuits

Seyed Armin Tajalli, Yusuf Leblebici

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on d ...

2008

Tri-State Buffer/Bus Driver Circuits in MOS Current-Mode Logic

Yusuf Leblebici, Stéphane Badel

In this paper, two circuits are proposed to implement tri-state buffers/bus drivers for MOS Current-Mode Logic digital circuits. The first is a switch-based, fully differential circuit, while the second is a voltage follower-based, pseudodifferential circu ...

IEEE2007

Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density

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An area and power optimization technique for CMOS bandgap voltage references

Hall sensor array

Improving the power-delay performance in subthreshold source-coupled logic circuits

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits

Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits

Power Distribution Paths for 3-D IC

A Novel Complex Gm-C IF Sub-Sampling Mixer

Pico-Watt Source-Coupled Logic Circuits

Tri-State Buffer/Bus Driver Circuits in MOS Current-Mode Logic

Current mode Alalog Kohonen Neural Network

An area and power optimization technique for CMOS bandgap voltage references

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits

Current mode Alalog Kohonen Neural Network

Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits

Tri-State Buffer/Bus Driver Circuits in MOS Current-Mode Logic

Hall sensor array

Improving the power-delay performance in subthreshold source-coupled logic circuits

Power Distribution Paths for 3-D IC

A Novel Complex Gm-C IF Sub-Sampling Mixer

Pico-Watt Source-Coupled Logic Circuits