Response Compaction in VLSI Testing

This lecture covers the analysis of the Circuit Under Test (CUT) response to test patterns in VLSI testing. It explains the challenges of handling large amounts of data generated by the CUT and introduces compaction techniques to reduce the data efficiently. The lecture discusses one's count compactor and transition count compactor methods, highlighting the principles and probability of fault masking. It also explores the concepts of parity checking, LFSR for response compaction, and multiple input signature register (MISR). The use of MISR for response compaction and the modular MISR example are presented, along with the analysis of LFSR signature and the built-in logic block observer (BILBO) for testing. The lecture concludes with discussions on test points and types of test points in VLSI testing.