Test of VLSI Systems: BIST and Response Compaction

This lecture covers the principles of Built-In Self-Test (BIST) techniques and Response Compaction in VLSI systems. It explains the use of Linear Feedback Shift Registers (LFSRs) for generating pseudo-random sequences and the benefits and drawbacks of BIST. The lecture also delves into Response Compaction techniques like One's Count Compactor, Transition Count Compactor, and Parity Checking. It discusses the implementation of Multiple Input Signature Register (MISR) and Built-In Logic Block Observer (BILBO) for efficient response analysis. The lecture concludes with a discussion on test points and their impact on fault coverage in VLSI testing.

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