Process Variation and Leakage Power

Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large Process Variation (PV). In the first chapter, we study ITRS semiconductor roadmap, state-of-the-art lithography techniques, and sub-65nm bulk-CMOS manufacturing technologies. Then, we discuss the necessity of low-power IC design. We talk about short-channel MOSFET modeling and we review the advantages and limitations of the future CMOS candidates, FD-SOI and FinFET. In chapter two, we study physical origins of the leakage current and we show why subthreshold leakage is usually the dominant leakage component in an optimized technology. Then, we discuss benefits and disadvantages of available leakage reduction techniques. We also show that high fan-in gates could be very energy efficient in sub-VT regime. In the third chapter, we study the physical origins of the variability. We study random dopant fluctuation, line edge roughness, random telegraph noise, metal work function variation, and other origins of the statistical variability. In chapter four, first we review conventional post-silicon variability compensation techniques, i.e. Adaptive Body Biasing (ABB) and Adaptive Supply Voltage (ASV). We discuss their limitations in the deca-nanometer regime. We see that in the planar transistor, body effect is diminishing with scaling; and in the emerging multi-gate transistors, body factor is almost zero. Then, we talk about reliability issues and see that increasing the VDD over the nominal voltage, reduces the IC lifetime exponentially. This imposes a major limitation on the ASV technique. We propose Adaptive Vgs Multiplexer (AVGS-Mux) technique for FPGA fabric design in chapter five. Proposed method controls the transistor current by the source voltage. It can provide ±1.6X control on the delay and ±7X exponential control on the sub-threshold and gate leakages in the switch-box, LUT, and interconnects at the same time. In TT corner, performance, leakage, and dynamic power overheads are almost zero. AVGS-Mux is a good replacement of ABB and ASV techniques in emerging manufacturing technologies which have very small body effect and cannot tolerate voltages higher than nominal VDD due to the reliability issues. We designed a full-custom mixed-signal circuit in 90nm CMOS technology to verify the idea. The measurement results match very well with simulation. In the last chapter, we show that in the logic circuits working at sub-nominal VDD, proper selection of the logic architecture and VDD together, can reduce the impact of the intra-die and inter-die variability on the timing significantly. First we show that s/µ ratio of the transistor current and delay strongly depends on the VDD. Then, we compare the PV sensitivity of Low-Power Slow (LP-S) architectures with High-Power Fast (HP-F) ones. The results show that for a given technology, equal power budget, and equal delay, LP-S circuits working at a higher VDD are less PV sensitive compared with HP-F circuits working at a lower VDD. Our method is particularly useful for combating intra-die random variability. We designed a full-custom mixed-signal circuit in 90nm CMOS technology to verify the proposed method. The measurement results show that the proposed method is actually more effective than what we see in simulation.