Threshold voltage | EPFL Graph Search

The threshold voltage, commonly abbreviated as Vth or VGS(th), of a field-effect transistor (FET) is the minimum gate-to-source voltage (VGS) that is needed to create a conducting path between the source and drain terminals. It is an important scaling factor to maintain power efficiency. When referring to a junction field-effect transistor (JFET), the threshold voltage is often called pinch-off voltage instead. This is somewhat confusing since pinch off applied to insulated-gate field-effect transistor (IGFET) refers to the channel pinching that leads to current saturation behaviour under high source–drain bias, even though the current is never off. Unlike pinch off, the term threshold voltage is unambiguous and refers to the same concept in any field-effect transistor. Basic principles In n-channel enhancement-mode devices, a conductive channel does not exist naturally within the transistor, and a positive gate-to-source voltage is necessary to create one such. The positi

III-V Nanowire Hetero-junction Tunnel FETs integrated on Si

Davide Cutaia

In the last decade the power consumption of electronic devices has increased for both static and active components. Following the Dennard's scaling rule, as long as the transistor sizes are reduced then the supply voltage (VDD) can also be scaled in order to increase the area density and maintain or improve the performances. However, scaling VDD and thus shifting the threshold voltage (Vth) of 60mV in a metal-oxide semiconductor field-effect transistor (MOSFET) increases the OFF state current (Ioff ) by a factor of 10 in the ideal case. The reason for this is that the inverse subthreshold slope (SS) in an ideal MOSFET is limited by the thermionic emission of electrons over a potential barrier, which has an intrinsic physical limit of 60mV/decade. To overcome this limit, novel device concepts have been proposed and the tunnel field-effect transistor (TFET) is one of the most promising because it resembles a MOSFET and should enable to achieve sub-60mV/dec SS, low Ioff and small VDD. The aim of this thesis is to investigate the potential of TFETs by the fabrication and characterization of InAs/Si as p-channel and InAs/GaSb as n-channel device for a complementary TFET technology. III-V nanowires are grown via metal-organic chemical vapor deposition (MOCVD) and are integrated on Si(100) substrates using a novel technique called template-assisted selective epitaxy (TASE), which enables the fabrication of vertical and lateral III-V hetero-structure TFETs. Sub-40nm nanowire cross-section InAs/Si p-TFETs and InAs/GaSb n-TFETs in-plane on Si are demonstrated for the first time. The InAs/Si p-TFETs exhibit state-of-the art performances with an ON state current (Ion) of 4uA/um at VGS=VDS=-0.5V, ON/OFF ratio of 1x10E5 with SSavg of 70-80mV/dec at room temperature. The InAs/GaSb n-TFETs have an order of magnitude larger Ion but the SS is limited by the non-optimized gate-stack on InAs channel and by the depletion of the undoped GaSb source. Different operation regimes of TFETs are investigated by temperature-dependent measurements,Wentzel-Kramers-Brillouin (WKB) modeling and TCAD simulations, indicating that the switching region for InAs/Si is dominated by the presence of traps at the hetero-junction. The abruptness of the band-edges in InAs/GaSb is studied by the extraction of the conductance slope in fabricated p-n and p-i-n tunnel diodes.

EPFL2016

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

Semiconductor nanowires are an emerging class of materials with great potential for applications in future electronic devices. The small footprint and the large charge-carrier mobilities of nanowires make them potentially useful for applications with high-integration density, but also to replace thin-film transistors in large-area electronics. This thesis investigates the use of wet-chemically grown ZnO nanowires for the fabrication of high-performance, low-voltage field-effect transistors (FETs). The first part of this thesis addresses the electrical characteristics of the wet-chemically grown ZnO nanowires. The as-grown ZnO nanowires are highly conductive due to a large charge-carrier concentration caused by dopants unintentionally incorporated into the ZnO nanowires during the synthesis. This large charge-carrier concentration makes it difficult to modulate the conductivity of the nanowires by an external electric field, so that the as-grown wires are not suitable for FETs. A post-growth annealing step is employed to dramatically reduce the charge-carrier concentration of the nanowires which makes it possible to fabricate FETs with useful characteristics. ZnO-nanowire FETs in a global back-gate geometry based on annealed ZnO nanowires have a transconductance of 300 nS, an on/off current ratio of 107 and a subthrehold slope of 500 mV/decade. The maximum field-effect mobility of the annealed ZnO nanowires is around 50 cm2/Vs. An important requirement to obtain good FET characterisitcs is to minimize the influence of the source and drain contact resistance on the total device resistance. The material used for the source and drain contacts in this thesis is aluminum. It is demonstrated that the use of a plasma treatment in the contact regions prior to the evaporation of the aluminum contacts can greatly influence the contact properties between ZnO and aluminum. An argon-plasma treatment locally increases the charge-carrier concentration in the ZnO. It is shown that the doping effect of the argon-plasma treatment can be exploited to reduce the contact resistance between alumiunm and ZnO and improve the electrical performance of the FETs. In the second part of this thesis, the influence of the ambient air on the electrical characteristics of the ZnO-nanowire FETs is investigated. The electrical conductivity of the FETs is strongly affected by the distinct atmospheric conditions, which makes it difficult to obtain reliable FET characteristics. The potential of a self-assembled monolayer (SAM) based on fluoroalkylphosphonic acid molecules to passivate the ZnO nanowires against the undesirable effects of the ambient and to stabilize the electrical performance of ZnO-nanowire FETs is demonstrated. The stabilizing effect is attributed to the formation of a densely packed, hydrophobic SAM on the surface of ZnO and aluminum oxide. The quality of the hydrophobic SAMs is confirmed by means of water-contact-angle measurements on SAM-covered ZnO single crystals that show a contact angle of more than 110°. The third part of this thesis is dedicated to the fabrication of high-performance ZnO-nanowire FETs with patterned metal top-gate electrodes. A top-gate fabrication process is developed that uses a very thin gate dielectric consisting only of an alkylphosphonic acid SAM that can be deposited from solution. The insulating quality of the SAM is investigated for top-gate FETs that utilize either gold or aluminum for the top-gate electrode. Gold top-gate FETs show a transconductance of 1 µS, an on/off current ratio of 107, and a steep subthreshold slope of 90 mV/decade. The thin gate dielectric makes it possible to operate the gold top-gate FETs at low voltages of 1 V and simultaneously reduces the undesired gate current by more than three orders of magnitude compared to gold top-gate FETs that have been fabricated without a gate dielectric (MESFETs). The gate current of the gold top-gate FETs with SAM gate dielectric is as low as 1 pA for gate-source voltages between -1 V and 0.5 V. When aluminum is used for the top-gate electrode, a hybrid dielectric is formed at the interface between the SAM and the aluminum, consisting of the SAM and a spontaneously formed aluminum oxide layer. Owing to the hybrid gate dielectric, the aluminum top-gate FETs are operated with gate currents below 1 pA for voltages up to 3 V. The top-gate fabrication process does not require temperatures above 160 °C, which makes it possible to fabricate FETs on unconventional substrates that cannot tolerate high temperatures, such as glass or flexible plastics. Integrated circuits on single ZnO nanowires that are fabricated on glass and plastic substrates are demonstrated. The maximum switching frequency of the inverters is 1 MHz.

EPFL2011

Contact resistance effects in organic n-channel thin-film transistors

Reinhold Rödel

Organic thin-film transistors (TFTs) have undergone tremendous progress in the past few years. Their great potential in terms of mechanical flexibility, light weight, low-cost and large-area fabrication makes them promising candidates for novel electronic products, such as sensor arrays, radio-frequency identification tags and flexible displays. For the realization of these applications and to improve their performance it is necessary to miniaturize organic TFTs to dimensions of a few micrometers or even less. However, with such aggressive scaling, the device physics becomes more and more important. Especially the contact resistance at and close to the interface between the organic semiconductor and the source/drain metal limits the performance of the organic TFTs at miniaturized dimensions. In this thesis, the contact properties of bottom-gate, top-contact n-channel organic transistors are investigated using the gated four-probe (GFP) technique. The TFTs employ the small-molecule semiconductor N,N'-bis-(1H,1H-heptafluorobutyl)-1,7-dicyano-perylene-3,4:9,10-tetracarboxylic diimide (PDI-FCN2) and are fabricated on flexible plastic substrates. The transistors are air-stable and can be operated at low voltages of about 3 V, owing to a thin hybrid gate dielectric composed of aluminum oxide and a self-assembled molecular monolayer. The GFP method enabled a detailed investigation of the influence of a multitude of factors, including the gate-source and drain-source voltages, the contact length, the temperature and the contact metal, on the contact resistance. The contact properties are found to be very sensitive to the thickness of the organic semiconductor layer. In transistors in which this layer is relatively thin, ohmic contact resistances as small as about 0.6 Ohm cm were measured. In transistors with a relatively thick organic semiconductor layer, device physics becomes more complex and the current-voltage characteristics of the contact become nonlinear. Space-charge limited currents are identified as the probable origin of this nonlinear behavior. The good performance of the PDI-FCN2 transistors allows the realization of simple integrated circuits. Flexible organic complementary ring oscillators are fabricated and signal propagation delays per stage as short as 6 µs are demonstrated at a supply voltage of 3.6 V.

EPFL2016

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

EPFL2011

III-V Nanowire Hetero-junction Tunnel FETs integrated on Si

Davide Cutaia

EPFL2016

Contact resistance effects in organic n-channel thin-film transistors

Reinhold Rödel

EPFL2016