Are you an EPFL student looking for a semester project?
Work with us on data science and visualisation projects, and deploy your project as an app on top of Graph Search.
An area- and power-optimized asynchronous 32x interleaved SAR ADC achieving 36 GS/s at 110mW and 1V supply on the interleaver and 0.9V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a power- and area optimized binary SAR ADC, and an area optimized clocked reference buffer with a tunable constant current source. It achieves 32.6 dB SNDR up to 3GHz and 31.6 dB up to 18 GHz input frequency and 98 fJ/conversion-step with a core chip area of 340x140 um2 in 32nm SOI CMOS technology.
David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi
David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Rafael Medina Morillas, Joshua Alexander Harrison Klein