Publication

Integrated ESOP Refactoring for Industrial Designs

Abstract

We present a multi-level logic refactoring algorithm based on exclusive sum-of-product (ESOP) expressions. ESOP expressions are two-level logic representation forms, similar to sum of -product (SOP) expressions. However, ESOPs use EXOR instead of OR operators. It has been shown that this allows ESOPs to be exponentially more compact than SOP expressions for important classes of functions. Our algorithm is based on a combination of ESOP collapsing, minimization, and refactoring. In EXOR-heavy logic, such as arithmetic units, it unlocks optimizations that may be outside the reach of SOP based methods. We show that our method is able to significantly improve upon logic optimization results, as compared to a similar SOP based flow. On a set of EXOR-heavy benchmarks, we reduce logic levels by up to 833% in the best case, and by 44.6% on average. Further, we are able to reduce logic network size by 21.4% on average. We have integrated our method into a commercial synthesis flow. On a set of 46 industrial benchmarks, the optimizations introduced by our algorithm improve design results after physical synthesis.

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Related concepts (34)
Logic optimization
Logic optimization is a process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. This process is a part of a logic synthesis applied in digital electronics and integrated circuit design. Generally, the circuit is constrained to a minimum chip area meeting a predefined response delay. The goal of logic optimization of a given circuit is to obtain the smallest logic circuit that evaluates to the same values as the original one.
Logic synthesis
In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool. Common examples of this process include synthesis of designs specified in hardware description languages, including VHDL and Verilog. Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs.
Canonical normal form
In Boolean algebra, any Boolean function can be expressed in the canonical disjunctive normal form (CDNF) or minterm canonical form, and its dual, the canonical conjunctive normal form (CCNF) or maxterm canonical form. Other canonical forms include the complete sum of prime implicants or Blake canonical form (and its dual), and the algebraic normal form (also called Zhegalkin or Reed–Muller). Minterms are called products because they are the logical AND of a set of variables, and maxterms are called sums because they are the logical OR of a set of variables.
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