Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes the data rates of interconnect standards continuously. The technology scaling has improved the I/O data rates and data processing power over the last decade. However, the bandwidth of the copper links has not been scaled similarly. Therefore, the need for advanced equalization techniques and high modulation orders has increased to be able to mitigate the high intersymbol interference that arises at high frequencies due to channel loss. All these techniques bring an increased power consumption for the serial links; therefore, the energy-efficiency of the wireline links is an important necessity to focus on in today's world.

In this thesis, we have investigated different design techniques to improve the energy-efficiency of the high-speed wireline serial links. First of all, the energy-efficiency of current-mode and voltage-mode transmitters (TXs) are compared. For this comparison, two TX prototypes that have low-voltage differential signaling and source-series-terminated (SST) drivers, to be used in a multi-channel analog-to-digital converter (ADC) system to transfer the ADC output data to a field-programmable gate array, are designed in 28 nm FD-SOI. The prototype TXs operate at 12.5 Gb/s which is the maximum data rate supported by the JESD204B standard, and the power consumption of the TXs is optimized for this data rate. Second, a comparative study, analyzing the potentials of pulse amplitude modulation (PAM) for implementing high-speed copper wireline links is presented. Different modulation orders (PAM-2, PAM-4, and PAM-8) have been simulated and their eye diagrams are compared for different channels and different data rates to understand the inherent limitations of these modulation schemes.

Then, a high-impedance driver technique is proposed for high-speed PAM-4 SST TXs. The proposed high-impedance driver technique provides a significant reduction in the capacitive load, decreases the high dynamic power consumption disadvantage of the SST TXs, and introduces 20% less power consumption for the whole TX compared to the conventional design. Measurement results show that the prototype PAM-4 TX with 4-tap feed-forward equalizer (FFE) in 28 nm FD-SOI achieves 2.4 pJ/bit energy-efficiency at 32 Gb/s data rate.

Finally, a very high-order modulation compatible TX and receiver analog front-end (RX AFE) system is presented to investigate the effect of the modulation order in energy-efficiency. Considering the equalization capability and the target moderate-loss channel, the optimum modulation order is decided with a modeling study. After that, the PAM-16 compatible SST TX and ADC-based RX AFE system is designed in 28 nm FD-SOI with the objective of minimizing the power consumption. The equalizer blocks, which are a continuous-time linear equalizer and a 2-tap FFE embedded in the ADC, both operate in the analog domain to bypass the disadvantages that high-order modulation brings. The TX consumes 26.85 mW while the RX AFE consumes 49.36 mW at 8 Gbaud. The corresponding energy-efficiency is 2.38 pJ/bit for the whole system with PAM-16 at 32 Gb/s data rate.