Engineering Breakdown Probability Profile for PDP and DCR Optimization in a SPAD Fabricated in a Standard 55nm BCD Process

CMOS Single-Photon Avalanche Diodes (SPADs) have broken into the mainstream by enabling the adoption of imaging, timing, and security technologies in a variety of applications within the consumer, medical and industrial domains. The continued scaling of technology nodes creates many benefits but also obstacles for SPAD-based systems. Maintaining and/or improving upon the high-sensitivity, low-noise, and timing performance of demonstrated SPADs in custom technologies or well-established CMOS image sensor processes remains a challenge. In this paper, we present SPADs based on DPW/BNW junctions in a standard Bipolar-CMOS-DMOS (BCD) technology with results comparable to the state-of-the-art in terms of sensitivity and noise in a deep sub-micron process. Technology CAD (TCAD) simulations along with analytical modelling are used to iterate through two versions of the proposed SPAD for improved detection efficiency. The result is an 8.8 m diameter SPAD exhibiting 1.2 cps/m2 DCR at 20C with 7 V excess bias. The improved structure obtains a PDP of 62 % and 4.2% at 530 nm and 940 nm, respectively. Afterpulsing probability is < 1 % and the timing response is 106 ps FWHM when measured with passive quench/recharge using external components.