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Publication
Are you an EPFL student looking for a semester project?
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This article presents a design-for-test methodology for embedded memories. The methodology relies on a fully random fault model of post-fabrication errors, which results in a low-overhead test strategy. The methodology's effectiveness is demonstrated on an embedded system with faulty memories.
Sandro Carrara, Ali Meimandi, Ata Jedari Golparvar, Sarah Tonello