Publications related to Multithreading (computer architecture)

SMoTherSpectre: Exploiting Speculative Execution through Port Contention

Babak Falsafi, Mathias Josef Payer, Atri Bhattacharyya

Spectre, Meltdown, and related attacks have demonstrated that kernels, hypervisors, trusted execution environments, and browsers are prone to information disclosure through micro-architectural weaknesses. However, it remains unclear as to what extent other ...

ACM2019

Duality in the Mechanism of Hexagonal ZnO/CuxO Nanowires Inducing Sulfamethazine Degradation under Solar or Visible Light

César Pulgarin, Juan Kiwi, Sami Rtimi, Jiajie Yu

This study presents the first evidence for the photocatalytic performance of ZnO/CuxO hexagonal nanowires leading to sulfamethazine (SMT) degradation. The chemical composition of the nanowires was determined by X-ray fluorescence (XRF). The sample with the ...

2019

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Boris Robert Grot, Siddharth Gupta

In a drive to maximize resource utilization, today's datacenters are moving to colocation of latency-sensitive and batch workloads on the same server. State-of-the-art deployments, such as those at Google, colocate such diverse workloads even on a single S ...

IEEE2019

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Paolo Ienne, Mikhail Asiatici

FPGAs rely on massive datapath parallelism to accelerate applications even with a low clock frequency. However, applications such as sparse linear algebra and graph analytics have their throughput limited by irregular accesses to external memory for which ...

ASSOC COMPUTING MACHINERY2019

Interleaving with coroutines: a systematic and practical approach to hide memory latency in index joins

Anastasia Ailamaki, Georgios Psaropoulos

Index joins present a case of pointer-chasing code that causes data cache misses. In principle, we can hide these cache misses by overlapping them with computation: The lookups involved in an index join are parallel tasks whose execution can be interleaved ...

2018

Multi-Arm Self-Collision Avoidance: A Sparse Solution for a Big Data Problem.

Aude Billard, Nadia Barbara Figueroa Fernandez, Seyed Sina Mirrazavi Salehian

In this work, we propose a data-driven approach for real-time self-collision avoidance in multi-arm systems. The approach consists of modeling the regions in joint-space that lead to collisions via a Self-Collision Avoidance (SCA) boundary and use it as a ...

2018

A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing

Paolo Ienne, Andrea Guerrieri, Sahand Kashani

FPGAs (Field Programmable Gate Array) are an attractive technology for high-speed data processing in space missions due to their unbeatable flexibility and best performance-to-power ratio in comparison to software. However FPGAs suffer from 3 major drawbac ...

IEEE2018

USSR: An UltraSound Sparse Regularization framework

Jean-Philippe Thiran, Yves Wiaux, Dimitris Perdios, Marcel Arditi, Adrien Georges Jean Besson, Florian Martinez

Ultrafast ultrasound (US) imaging uses unfocused waves to insonify the whole medium of interest at once, allowing pulse-echo US imaging to achieve very high frame rates, at the cost of a lower image quality. In this paper, we present USSR, an UltraSound Sp ...

Ieee2017

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

Rachid Guerraoui, Aleksandar Dragojevic, Georgios Chatzopoulos

This article presents ESTIMA, an easy-to-use tool for extrapolating the scalability of in-memory applications. ESTIMA is designed to perform a simple yet important task: Given the performance of an application on a small machine with a handful of cores, ES ...

2017

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Multithreading (computer architecture)

SMoTherSpectre: Exploiting Speculative Execution through Port Contention

Duality in the Mechanism of Hexagonal ZnO/CuxO Nanowires Inducing Sulfamethazine Degradation under Solar or Visible Light

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Interleaving with coroutines: a systematic and practical approach to hide memory latency in index joins

Multi-Arm Self-Collision Avoidance: A Sparse Solution for a Big Data Problem.

A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing

Towards a scalable quantum computer

USSR: An UltraSound Sparse Regularization framework

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

Graph Chatbot

Chat with Graph Search

A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

ESTIMA: Extrapolating ScalabiliTy of In-Memory Applications

Multi-Arm Self-Collision Avoidance: A Sparse Solution for a Big Data Problem.

USSR: An UltraSound Sparse Regularization framework

Towards a scalable quantum computer

Duality in the Mechanism of Hexagonal ZnO/CuxO Nanowires Inducing Sulfamethazine Degradation under Solar or Visible Light

Interleaving with coroutines: a systematic and practical approach to hide memory latency in index joins

SMoTherSpectre: Exploiting Speculative Execution through Port Contention