Concept

Orthogonal instruction set

Related publications (14)

Exploiting NVM in Large-scale Graph Analytics

Data center applications like graph analytics require servers with ever larger memory capacities. DRAM scaling, how- ever, is not able to match the increasing demands for ca- pacity. Emerging byte-addressable, non-volatile memory technologies (NVM) offer a ...

2015

1kHz 2D silicon retina motion sensor platform

Dario Floreano

This paper proposes an optical motion sensor aimed towards small robotic platforms. It incorporates a 20×20 pixel continuous-time CMOS silicon retina vision sensor with pixels that have local gain control and adapt to background lighting and a DSP microcon ...

IEEE2014

Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing

David Atienza Alonso, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

A multi-core architecture with ultra-low power consumption is needed for a wide variety of applications, especially in the bio-medical domain. In this patent, an ultra-low power multi-core architecture is presented: it is composed of one or more cores, sev ...

2014

Low Power Wake-up Receiver

Lorenz Flavio Schmid

With more devices becoming mobile, power consumption of communication becomes crucial. Wake-up receivers present an energy-ecient way of detecting incoming transmissions while at the same time the main radio can be fully powered down. After detection the r ...

2014

Carbon Nanotube Crossed Junction by Two Step Dielectrophoresis

Mihai Adrian Ionescu, Anupama Arun

The crossed junction formed between a multi walled carbon nanotube (MWCNT) and a bundle of single walled carbon nanotube (SWCNT) is investigated. The junction is fabricated by orthogonally assembling the MWCNT and SWCNT by a two-step dielectrophoresis proc ...

2011

Dataflow Programming for Systems Design Space Exploration for Multicore Platforms

Christophe Lucarz

Nowadays processing systems are asked to support increasing complex and demanding high-performance applications, especially in the signal processing and video processing domains. The design of these systems are becoming extremely challenging because of sev ...

EPFL2011

Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Samuel Burri, Philip Brisk

Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include Architecturally Visible Storage (AVS), compiler-controlled memories accessible exclus ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

Static Analysis of x86 Executables

Johannes Kinder

This dissertation is concerned with static analysis of binary executables in a theoretically well-founded, sound, yet practical way. The major challenge is the reconstruction of a correct control flow graph in presence of indirect jumps, pointer arithmetic ...

Technische Universität Darmstadt2010

Memory Organization and Data Layout for Instruction Set Extensions with Architecturally Visible Storage

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Panagiotis Athanasopoulos

Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional units (CFUs). Adoption of the optimal ISE for an application would, in many cas ...

2009

The Semantics of Progress in Lock-Based Transactional Memory

Rachid Guerraoui, Michal Kapalka

Transactional memory (TM) is a promising paradigm for concurrent programming. Whereas the number of TM implementations is growing, however, little research has been conducted to precisely define TM semantics, especially their progress guarantees. This pape ...

ACM2009

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