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Die shrink

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A start-up boosting circuit with 133× speed gain for 2-transistor voltage reference

Monolithic technology for silicon nanowires in high-topography architectures

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes

Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design

A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

Approximate 32-Bit Floating-Point Unit Design with 53% Power-Area Product Reduction

Sub-electron CIS noise analysis in 65 nm process

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS