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The prospective use of upcoming nanometer CMOS technology nodes (65nm, 45nm, and beyond) in bio-electronic interfaces is raising a number of important issues concerning circuit architectures and design. In particular, the advantages of scaling and higher d ...
A new programmable neighborhood mechanism for the Winner Takes Most (WTM) self-organizing Kohonen map has been proposed in this paper. Described circuit is an asynchronous solution, which does not require the controlling clock generator. The winning neuron ...
The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data co ...
Multiplexers are one of the most important elements in readout front-end ASICs for multi-element detectors in medical imaging. The purpose of these ASICs is to detect signals appearing randomly in many channels and to collect the detected data in an ordere ...
One of the biggest challenges that are facing the Very Large Scale Integrated Circuits (VLSI) technologies today is the significant performance gap (3× to 9×) between full custom circuits and Application Specific Integrated Circuits (ASICs) designed in the ...
Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic synthesisers, which play a fundamental role in design today, play a minor ro ...
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An ultra low power 8-bit current-mode successive approximation (SAR) analog-to-digital (ADC) converter for Wireless Sensor Network (WSN) applications is presented. The proposed ADC contains a new asynchronous clock generator, which works only during data p ...
In this paper a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can be realized. The ...
In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can ...
In this paper, we study the operation of MOS current-mode logic (MCML) gates at lower-than-nominal supply voltages.We show that power can be traded for speed by reducing the supply voltage below the nominal value, while the power-delay product stays nearly ...