Microprocessor | EPFL Graph Search

A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, and control circuitry required to perform the functions of a computer's central processing unit (CPU). The IC is capable of interpreting and executing program instructions and performing arithmetic operations. The microprocessor is a multipurpose, clock-driven, register-based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, and provides results (also in binary form) as output. Microprocessors contain both combinational logic and sequential digital logic, and operate on numbers and symbols represented in the binary number system. The integration of a whole CPU onto a single or a few integrated circuits using Very-Large-Scale Integration (VLSI) greatly reduced the cost of processing power. Integrated

Enhanced-performance integrated Resonant Switched-Capacitor and Buck DC-DC converters for application in extreme radiation and magnetic field environments

Giacomo Ripamonti

DC-DC converters based on Application Specific Integrated Circuits (ASICs) have been developed in this doctoral work for the High-Luminosity Large Hadron Collider (HL-LHC) experiments at CERN. They step down the voltage from a 2.5 V line and supply a load current up to 3 A. The main focus has been the miniaturization of the converters while maintaining high efficiency, together with the improvement of the dynamic performance and the minimization of the impact of substrate parasitic devices. These are challenges that industry and research are facing to power modern microprocessors, with the aim of minimizing the system volume, cost and power consumption, while guaranteeing good regulation performance. Miniaturization is a key requirement for application in the HL-LHC experiments, since any added material is detrimental for the physics performance. In addition, the converters must be tolerant to a high magnetic field (up to 4 T) and to ultra-high levels of radiation. Tolerance to the magnetic field is achieved by employing air-core inductors (which are the bulkiest components on the board), while radiation-hard ASICs have been designed in this work in a commercial 130 nm CMOS technology by extensively applying hardening by design techniques. Converters using two different architectures have been designed: a buck converter, which had been identified in a previous work as a good option to achieve high efficiency and low mass, and a Resonant Switched-Capacitor (ReSC) converter, which can further increase the power density while keeping high efficiency. A novel dual-edge pulse width modulator for the buck converter that has improved dynamic performance compared to conventional solutions has been designed and implemented. Its small-signal response has been modeled, and the model has been validated by measurements. In addition, this thesis proposes an integrated system that monitors in real-time the voltage stress experienced by the devices of the buck converter and adjusts its operation accordingly, in order to guarantee the required reliability, while maximizing the efficiency. The main building block of this system has been designed and has proved to be fully functional. A substrate-currents-aware characterization method that allows the evaluation of the impact of substrate parasitic devices on the circuit performance and reliability has been also devised, and it has been applied to select the best floor-plan for the buck converter. A novel control scheme that optimizes the efficiency of the ReSC converter for the whole load current range by adopting different operation modes has been proposed and implemented. This thesis reports the steady-state analysis of each mode and a small-signal model for one of them. The buck converter uses a 100 nH inductor, and the last prototype shows a peak efficiency of 88.4% for the 2.5 V-to-1.2 V conversion. It complies with the radiation specifications, and mass production will soon start. The designed prototype ReSC converter employs a 12 nH inductor, and its area occupancy and thickness are respectively 20% and 55% lower than the buck. Its efficiency is larger than that of the buck converter in a range of conversion ratios and load currents, reaching a peak efficiency of 91.4% for the 2.5 V-to-1.2 V conversion. Radiation tests have highlighted that the converter complies with Total Ionizing Dose specifications. By introducing a few improvements, a future prototype could be close to production readiness.

EPFL2020

Dynamically Trading Frequency for Complexity in a GALS Microprocessor

Microprocessors are traditionally designed to provide “best overall” performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques that save energy by “downsizing” hardware resources that are underutilized by the current application phase. Others have proposed a different energy-saving approach: dividing the processor into domains and dynamically changing the clock frequency and voltage within each domain during phases when the full domain frequency is not required. What has not been studied to date is how to exploit the adaptive nature of these approaches to improve performance rather than to save energy. In this paper, we describe an adaptive globally asynchronous, locally synchronous (GALS) microprocessor with a fixed global voltage and four independently clocked domains. Each domain is streamlined with modest hardware structures for very high clock frequency. Key structures can then be upsized on demand to exploit more distant parallelism, improve branch prediction, or increase cache capacity. Although doing so requires decreasing the associated domain frequency, other domain frequencies are unaffected. Our approach, therefore, is to maximize the throughput of each domain by finding the proper balance between the number of clock periods, and the clock frequency, for each application phase. To achieve this objective, we use novel hardware-based control techniques that accurately and efficiently capture the performance of all possible cache and queue configurations within a single interval, without having to resort to exhaustive online exploration or expensive offline profiling. Measuring across a broad suite of application benchmarks, we find that configuring our adaptive GALS processor just once per application yields 17.6% better performance, on average, than that of the “best overall” fully synchronous design. By adapting automatically to application phases, we can increase this advantage to more than 20%.

2004

Improving Application Performance by Dynamically Balancing Speed and Complexity in a GALS Microprocessor

2003

Enhanced-performance integrated Resonant Switched-Capacitor and Buck DC-DC converters for application in extreme radiation and magnetic field environments

Giacomo Ripamonti

EPFL2020

Dynamically Trading Frequency for Complexity in a GALS Microprocessor

2004