Publications related to Delay-line memory

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi

The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

2024

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Andreas Peter Burg, Robert Giterman, Halil Andac Yigit, Emmanuel Nieto Casarrubias

Gain-cell embedded DRAM (GC-eDRAM) is a high-density logic-compatible alternative to conventional static random-access memory (SRAM) and embedded DRAM (eDRAM). However, GC-eDRAM suffers from a reduced data retention time (DRT) at deeply-scaled process node ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Flexure pivot based system

Simon Nessim Henein, Loïc Benoît Tissot-Daguette, Benoît Dagon, Michal Stanislaw Smreczak

Flexure pivot based system (1) being one of: a force sensor, a force limiting device arranged to exert a predetermined threshold force, a torque limiting device arranged to exert a predetermined threshold torque, a programmable mechanical memory, or an acc ...

2022

Adaptive table placement in NUMA architectures

Anastasia Ailamaki, Iraklis Psaroudakis

Techniques and solutions are provided for performing adaptive database table placement in a non-uniform memory access (NUMA) architecture. The adaptive table placement can occur in response to changing workloads on the NUMA nodes. For example, if a particu ...

2022

Associativity-agnostic in-cache computing memory architecture optimized for multiplication

David Atienza Alonso, Marina Zapater Sancho, Marco Antonio Rios

A random access memory array including a plurality of local memory group ways, each local memory group way including, a plurality of local memory groups, each local memory group including, a memory column including a plurality of memory cells, a pair of lo ...

2021

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) w ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as ...

IEEE2020

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Delay-line memory

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Flexure pivot based system

Adaptive table placement in NUMA architectures

Low Noise Clock Generation: Modeling, Analysis and Implementation

Associativity-agnostic in-cache computing memory architecture optimized for multiplication

Gain-Cell Embedded DRAMs: Modeling and Design Space

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

Gain-Cell Embedded DRAMs: Modeling and Design Space

Graph Chatbot

Chat with Graph Search

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Low Noise Clock Generation: Modeling, Analysis and Implementation

Associativity-agnostic in-cache computing memory architecture optimized for multiplication

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Flexure pivot based system

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Gain-Cell Embedded DRAMs: Modeling and Design Space

Gain-Cell Embedded DRAMs: Modeling and Design Space

Adaptive table placement in NUMA architectures

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space