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Fully-Homomorphic Encryption (FHE) offers powerful capabilities by enabling secure offloading of both storage and computation, and recent innovations in schemes and implementations have made it all the more attractive. At the same time, FHE is notoriously ...
Utilization of edge devices has exploded in the last decade, with such use cases as wearable devices, autonomous driving, and smart homes. As their ubiquity grows, so do expectations of their capabilities. Simultaneously, their formfactor and use cases lim ...
Recently, organic-inorganic halide perovskite (OHP) has been suggested as an alternative to oxides or chalcogenides in resistive switching memory devices due to low operating voltage, high ON/OFF ratio, and flexibility. The most studied OHP is 3-dimensiona ...
Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...
This paper presents a die-level post-CMOS processing protocol for multi-layer homogeneous 3D integration with adhesive bonding technique using parylene-C as an intermediate bonding layer and sidewall passivation material. This protocol was used to fabricat ...
Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each h ...
2016
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In the conventional von Neumann (VN) architecture, data—both operands and operations to be performed on those operands—makes its way from memory to a dedicated central processor. With the end of Dennard scaling and the resulting slowdown in Moore’s law, th ...
Springer India2017
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In this work, a chip-level post-CMOS processing protocol for 3D integration is presented to achieve multilayer stacking. This protocol includes TSV formation on the top chip, bonding the chips on top of each other, and finally the electrical connection pro ...
2014
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This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple ...
Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolv ...
