Personal digital assistant | EPFL Graph Search

A personal digital assistant (PDA), also known as a handheld PC, is a variety mobile device which functions as a personal information manager. PDAs have been mostly displaced by the widespread adoption of highly capable smartphones, in particular those based on iOS and Android, seeing a rapid decline in use after 2007. A PDA has an electronic visual display. Most models also have audio capabilities, allowing usage as a portable media player, and also enabling many of them to be used as telephones. By the early 2000s, nearly all PDA models had the ability to access the Internet, intranets or extranets via Wi-Fi or Wireless WANs, and generally include a web browser. Sometimes, instead of buttons, PDAs employ touchscreen technology. The first PDA, the Organiser, was released in 1984 by Psion, followed by Psion's Series 3, in 1991. The latter began to resemble the more familiar PDA style, including a full keyboard. The term PDA was first used on January 7, 1992 by Apple Inc. CEO John

On-Chip Digital Background Calibration of Pipelined Analog-to-Digital Converters using Digital Assistance to support Nonlinear Residue Amplification

Thomas Liechti

This thesis describes a novel digital background calibration scheme for pipelined ADCs with nonlinear interstage gain. Errors caused by the nonlinear gains are corrected in real-time by adaptively post-processing the digital stage outputs. The goal of this digital error correction is to improve the power efficiency of high-precision analog-to-digital conversion by relaxing the linearity and matching constraints on the analog pipeline stages and compensating the resulting distortion through digital post-processing. This approach is motivated by the observation that technology scaling reduces the energy cost of digital signal processing and at the same time makes high-precision analog signal processing harder because of reduced intrinsic device gain and reduced voltage headroom. In particular, the proposed calibration approach enables the use of power efficient circuits in noise-limited high-resolution, high-speed converters. Alternative stage circuit topologies that are more power efficient than their traditional counterparts are typically too nonlinear and too sensitive to temperature and bias variations to be employed in the critical stages of such converters without adaptive error correction. The proposed calibration scheme removes the effects of nonlinear interstage gain, sub-DAC nonlinearity, and mismatch between reference voltages of different stages. Gain errors and reference voltage mismatch are continuously tracked during normal operation and may thus be time-varying. Sub-DAC nonlinearity is assumed to be constant. A method to characterize the time-invariant non-ideal sub-DAC characteristics during an initial one-time offline calibration phase is proposed. Because the method only uses the existing uncalibrated analog hardware, it can only determine the relative sizes of the DAC error terms. One or two scale factors per sub-DAC remain to be estimated by the adaptation algorithm used to track the time-varying gain parameters. Because the scale factor is constant, it can be excluded from adaptation after its estimate has converged. This offline characterization of sub-DACs ensures that the entire characteristic of all sub-DACs can be estimated, and that calibration of DAC errors can be permanently turned off after initial convergence. Furthermore, it eliminates degrees of freedom in the error correction function, and fixes the gain of the calibrated ADC. The digital postprocessor linearizes the ADC transfer characteristic by applying an adaptive inverse model of the analog signal path to the digital outputs of the pipeline stages. The model uses piecewise linear (PWL) functions to approximate the inverse of the nonlinear stage gains. Previously reported background calibration methods are limited to low-order polynomial gain models. The PWL model is more general than low order polynomial models. The analog signal path can thus be optimized for power efficiency without any constraint on high order distortion. The previously reported split-ADC architecture is used to enable background adaptation of the error correction parameters during normal converter operation and without requiring an accurate reference ADC. The converter to be calibrated is split into two nominally identical channels, both channels processing the same input signal. The average of the outputs of the two channels is used as overall output. The difference of the channel outputs is used as an error signal. The mean-square value of this error signal serves as the performance function that is minimized by the adaptation algorithm. Because two non-ideal ADCs are used as reference channels for each other, precautions are needed to avoid that the adaptation algorithm simply equalizes the transfer characteristics of the two ADCs. The effect of the flexible gain model on these parasitic solutions is analyzed. A previously reported method to eliminate parasitic solutions in the case of linear gains is modified to also work with arbitrary nonlinear gain. A simplified version of the normalized least-mean-squares (NLMS) algorithm is used for parameter adaptation. Normalization assumes that the performance function is quadratic in the parameters, which is almost true because the channel output difference is almost linear in the error correction parameters. Because a low-noise reference signal is used, the LMS loop does not need to filter out noise. The normalization in conjunction with the low-noise reference signal significantly mitigates the convergence speed versus steady-state error trade-off. Heuristic strategies to control the NLMS algorithm are proposed to address identified weaknesses of the basic adaptation algorithm. The main benefits of the heuristic control are faster initial convergence and faster recovery from transient disturbances. Fast initial convergence is achieved by gradually increasing the granularity of the PWL gain models. Fast recovery after fast parameter changes is achieved by selectively reducing the search space for certain samples. A possible architecture for a hardware implementation of the postprocessor is analyzed to demonstrate the practicability of the proposed digital error correction scheme, and to propose detailed architectures for critical blocks. The analysis concludes that using the proposed architecture, the hardware implementation poses no specific difficulty in terms of area, power, or design complexity. A novel approach for adaptive nonlinear digital error correction for pipelined ADCs is proposed. The error correction models amplifier nonlinearity as a general piecewise linear function for maximum flexibility. The algorithm can be implemented using simple arithmetic and a small amount of memory only.

EPFL2012

Architecture of a Real-Time Platform Independant GPS L1 Software Receiver

Personal digital assistants or mobile phones applications are not anymore restricted to multimedia or wireless communications, but have been extended to handle Global Positioning System (GPS) functionalities. Consequently, the growing market of GPS capable mobile devices is driving the interest of software receiver solutions as they provide several advantages with respect to traditional hardware implementations. First, they share the same system resources such as the processor, embedded memory and power with other system units, reducing both the size and the costs of their integration. Second, they can be easily reprogrammed – via a firmware update – for incorporating the latest developments, such as the exploitation of the future satellites signals or some improved multipath mitigation techniques. Finally, they offer a more flexible solution for rapid research and development as compared to conventional hardware receivers where the chip design is fixed and obtained after a long integration process. With the increasing performance of modern processors, it becomes now feasible to implement in software a multi-channel GPS receiver operating in real-time. However, a major problem with the software architecture is the large computing resources required for the digital signal processing. Former studies have demonstrated that a straightforward transposition of traditional hardware based architectures into software would lead to an amount of integer operations which is not suitable for today's fastest computers. From this observation, several strategies have been proposed in the literature in order to reduce the complexity of the receiver operations. The first one relies on the utilization of advanced microprocessor instructions set which provides the capability of processing vectors of data by operating on multiple integer values at the same time. This results in significant gains in execution speed, but also severely limits the portability of the code, since the operations are tied to specific processors architectures. Another alternative consists in exploiting the native bitwise representation of the signal. The data bits are stored in separate vectors on which logical parallel operations can be performed. The objective is to take advantage of the universality, high parallelism, and speed of the bitwise operations for which a single integer operation translates into a few simple parallel logical relations. However, the inherent drawback of the bitwise processing is the lack of flexibility as the complexity becomes bit-depth dependent. This thesis has been carried out in the framework of a two-year industrial project (2007-2009) in collaboration with U-blox AG in Thalwil. It aimed to the realization of a multi-channel, platform-independent real-time GPS L1 software receiver. The main challenge of this project consisted in providing real-time performances while keeping the portability of the code to make the receiver suitable for any type of software implementation. In that sense, new techniques and algorithms have been developed for optimizing the processing chain in order to lower the processor load. The main idea consists in regrouping data which share the same characteristics, and process them in batches instead of sequentially. This way, it becomes possible to progressively reduce the data throughput and consequently the amount of operations to perform. A completely new receiver architecture has been proposed and validated through the realization of a functional prototype, thus demonstrating the feasibility of the concept.

EPFL2010

Performances of a New Correlation Algorithm for a Platform-independent GPS Software Receiver

Marcel Baracchi Frei, Cyril Botteron, Pierre-André Farine

Personal Digital Assistants (PDA’s) or mobile phones applications are not anymore restricted to wireless communications or multimedia, but have been extended to handle Global Navigation Satellite System (GNSS) functionalities. Consequently, the growing market of GNSS capable mobile devices is driving the interest of software solutions as they provide several advantages with respect to the conventional hardware architectures currently implemented in the mass market receivers. First, they share the same system resources such as the processor, embedded memory and power with other system units, reducing both the size and the costs of their integration. Second, they can be easily reprogrammed - via firmware updates - for incorporating the latest developments, such as the exploitation of the future GNSS signals or some improved multipath mitigation techniques. Finally, they offer a more flexible solution for rapid research and development as compared to conventional hardware receivers where the chip design is fixed and obtained after a very long integration process. This paper will first introduce the challenges of the software implementation of a GNSS receiver, with a main focus given to the base-band processing and the correlation issues. It will then describe the already existing solutions with their respective advantages and drawbacks, and provide an estimation of their complexity in term of computational load. From this, a new developed algorithm will be introduced, and its performances in term of integer operations needed to perform the correlation analyzed and compared to the other solutions.

Inst Navigation, 815 15Th Th St Nw, Ste 832, Washington, Dc 20005 Usa2009