Concept

NAND gate

Related publications (108)

Non-LUT field-programmable gate arrays

Paolo Ienne, Grace Zgheib, David Novo Bruna, Hadi Parandeh Afshar

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

2014

A Conjoined Electron and Thermal Transport Study of Thermal Degradation Induced During Normal Operation of Multigate Transistors

A 3-D full-band particle Monte Carlo (MC) simulator, with full electron and phonon dispersion and a 2-D quantum correction is self-consistently coupled to a phonon MC simulator. The coupling entails feeding the phonon data obtained from the 3-D electrical ...

Ieee-Inst Electrical Electronics Engineers Inc2014

Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Michele De Marchi

Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential fo ...

Institute of Electrical and Electronics Engineers2014

Self-Checking Ripple-Carry Adder with Ambipolar Silicon Nanowire FET

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Ogün Türkyilmaz

For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to perma ...

2013

Dual-threshold-voltage configurable circuits with three-independent gate silicon nanowire FETs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang

We extend ambipolar silicon nanowire transistors by using three independent gates and show an efficient approach to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying dif ...

2013

Ultra low power NEMFET based logic

Mihai Adrian Ionescu, Antonios Bazigos, Surya Shankar Dan

In this paper, we introduce a Nano-Electro-Mechanical Field Effect Transistor (NEMFET) based logic family tailored to the implementation of low speed and ultra low energy functional units and processors. Basic Boolean gates implemented with NEMFETs only ar ...

IEEE2013

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Shashi Kanth Bobba, Michele De Marchi

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics sim ...

2013

Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic

Mihai Adrian Ionescu, Didier Bouvet, Mohammad Najmzadeh

In this paper, we report formation of GAA buckled dual Si nanowire MOSFETs including two sub-80 nm Si cores on bulk Si using 0.8 mu m optical lithography and local oxidation for the first time. 0.833 GPa uniaxial tensile stress is measured in the buckled s ...

Elsevier Science Bv2013

Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: a Robustness Study

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Hassan Ghasemzadeh Mohammadi

Vertically-stacked Silicon NanoWire FETs (SiN- WFETs) with gate-all-around control are the natural and most advanced extension of FinFETs. At advanced technology nodes, due to Schottky contacts at channel interfaces, devices show an ambipolar behavior, i.e ...

2013

FinFET integrated low-power circuits for enhanced sensing applications

Mihai Adrian Ionescu, Antonios Bazigos, Alexandru Rusu, Sara Rigante, Paolo Livi

This work presents different circuit architectures that combine sensing and signal readout functions. The basic building block is a Fin Field-Effect Transistor (Fin-FET) used as both sensor and metal gate transistor. Moreover, a hybrid partially gated FinF ...

Elsevier2013

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.