Design for testing

Applied sciences
Computer engineering
Hardware engineering
Application-specific integr...

Related publications (25)

About
Privacy
Disclaimer

Graph Chatbot

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Paolo Ienne, Barbara Jobstmann, David Novo Bruna, Andrew James Becker, Mohsen A A Ewaida

Functional verification occupies a significant amount of the digital circuit design cycle. In this paper, we present a novel approach to improve circuit debugging which not only localizes errors with high confidence, but can also provide semantically-meani ...

Springer2015

System Design Automation: Challenges and Limitations

Joseph Sifakis

Electronic design automation (EDA) has enabled the integrated circuit industry to sustain exponentially increasing product complexity growth until today, while maintaining consistent product development timeline and costs. We argue that the success of EDA- ...

Ieee-Inst Electrical Electronics Engineers Inc2015

New Data Structures and Algorithms for Logic Synthesis and Verification

Luca Gaetano Amarù

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effec ...

EPFL2015

A Circuit Synthesis Flow for Controllable-Polarity Transistors

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Double-Gate (DG) controllable-polarity Field-Effect Transistors (FETs) are devices whose n- or p- polarity is on-line configurable by adjusting the second gate voltage. Such emerging transistors have been fabricated in silicon nanowires, carbon nanotuges a ...

Institute of Electrical and Electronics Engineers2014

Nanowire systems: technology and design (invited paper)

Giovanni De Micheli, Davide Sacchetto, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Shashi Kanth Bobba, Michele De Marchi

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

Royal Soc2014

Cell Transformations and Physical Design Techniques for 3D Monolithic Integrated Circuits

Giovanni De Micheli, Shashi Kanth Bobba

3D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. In 3DMI technology the 3D contacts, connecting different active layers, are in the order of few 100 nm. Given the advantage of ...

2013

A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic ...

IEEE/ACM Press2013

Compressive Image Acquisition in Modern CMOS IC Design

Pierre Vandergheynst, Alexandre Schmid, Yusuf Leblebici, Mahdad Hosseini Kamal, Nikola Katic

Compressive Sampling (CS) offers bandwidth, power and memory size reduction compared to conventional (Nyquist) sampling. However, very few Integrated Circuit (IC) designs based on CS exist due to the missing link between the well-established CS theory on o ...

Wiley-Blackwell2013

Column-Separated Compressive Sampling Scheme for Low Power CMOS Image Sensors

Pierre Vandergheynst, Alexandre Schmid, Mustafa Kilic, Yusuf Leblebici, Mahdad Hosseini Kamal, Nikola Katic

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The scheme utilizes an identical pseudo-random sequence for every image column, therefore reducing in-pixel hardware complexity and allowing measurement ...

IEEE2013

Power-Efficient CMOS Image Acquisition System based on Compressive Sampling

Pierre Vandergheynst, Alexandre Schmid, Mustafa Kilic, Yusuf Leblebici, Mahdad Hosseini Kamal, Nikola Katic

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The prototype design is implemented in a 0.18um standard CMOS technology and utilizes compressed acquisition to boost the overall power efficiency. Spec ...

IEEE2013

Page 2 of 3