Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
In the present work a punch-through impact ionization MOSFET (PIMOS) is presented, which exploits impact ionization in low-doped body-tied [Omega]- and tri-gate structures to obtain abrupt switching (3-10 mV/decade) combined with a hysteresis in the ID(VDS ...
The earliest ideas of the polaron recognized that the coupling of an electron to ionic vibrations would affect its apparent mass and could effectively immobilize the carrier (self-trapping). We discuss how these basic ideas have been generalized to recogni ...
During atomic layer deposition of high permittivity (high-k) metal oxide gate dielectrics, an interfacial layer (IL) containing SiOx between high-k dielectric and Si substrate is almost unavoidable. However, an Al(CH3)(3) (TMA) pretreatment for 3600 s on H ...
The perovskite SrHfO3 can be a potential candidate among the high-permittivity materials for gate oxide replacement in future metal-oxide semiconductor field-effect transistor technology. Thin films of SrHfO3 were grown by molecular beam epitaxy and compar ...
In this paper, the RF Breakdown power threshold in arbitrary complex components based on rectangular waveguide technology is investigated. In particular, multipactor (in vacuum) and corona discharge (close to the Paschen curve minimum) are analyzed. The ob ...
Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always be ...
Reliable split C(V) measurements are shown to be feasible on ultra-thin oxides (down to 1.2 nm) by using relatively small area MOSFETs (typically 100 mum(2)). To this end, specific correction procedures for parasitic parallel capacitances and gate leakage ...
Main stream bulk CMOS and the variants of silicon-on-insulator (SOI) CMOS technologies are discussed with respect to testing for the quiescent current of mixed-signal integrated SOI circuits. The 2-3 times lower static power consumption in fully depleted C ...
A process to fabricate functional polysilicon structures above large (4 x 4 mm(2)) thin (200 nm), very flat LPCVD silicon rich nitride membranes was developed. Key features of this fabrication process are the use of low-stress LPCVD silicon nitride, sacrif ...
This work reports on thermally isolated electronic components for gas sensing applications. The device is composed of an array of 4 MOSFET, a diode and a semiconductor resistor integrated on a micro-hotplate, which is fabricated using bulk micromachining o ...
