Publications related to Zero ASIC

Tradeoffs in Low-Power Accelerators Design for Large-Scale Interferometers

David Atienza Alonso, Miguel Peon Quiros, Denisa-Andreea Constantinescu, Benoît Walter Denkinger

Large-scale scientific infrastructures like SKAO—the world’s largest radio observatory for the coming decades—are generating massive-scale data streams of multi-Tb/s to be processed using complex interferometry algorithms. Concretely, SKAO is expected to g ...

2023

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Anastasia Ailamaki, Periklis Chrysogelos, Hamish Mcniece Hill Nicholson, Syed Mohammad Aunn Raza

Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...

2023

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Paolo Ienne, Andrea Guerrieri, Sahand Kashani

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing ...

2019

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow

Edoardo Charbon, Francesco Regazzoni

This work proposes the first fine-grained configurable cell array specifically tailored for the implementation of cryptographic algorithms that can be configured using widely adopted hardware description languages. Our solution can be added as a small, cry ...

IEEE2018

Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures

Edoardo Charbon, Harald Arjan Robert Homulle

Quantum computers enable a massive speed-up in calculations, thanks to the nature of quantum operations. To unlock quantum computation, a classical system infrastructure is required for the control of qubits and processing of their data. While qubits are g ...

2018

Abstracting Multi-Core Topologies with MCTOP

Rachid Guerraoui, Vasileios Trigonakis, Georgios Chatzopoulos

Portability and efficiency are usually antagonists in multi-core computing. In order to develop efficient code, one needs to take into account the topology of the target multi-cores (e.g., for locality). This clearly hampers code portability. In this paper ...

ACM Press2017

Analysis of CMS noise reduction for 65 nm CIS

Christian Enz, Assim Boukhayma, Raffaele Capoccia

This work explores the combination of a downscaled technology with in-pixel source-follower (SF) optimization, a high column-level gain and an analog implementation of Correlated-Multiple-Sampling (CMS) for noise reduction of CIS readout chains. Transient ...

2017

High-Precision Performance Estimation of Dynamic Dataflow Programs, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska

An important challenge for a dataflow designer is to efficiently explore the design space in order to find a set of configurations that satisfy the defined objective function. The exploration directions may involve the partitioning, scheduling and buffer d ...

2016

Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

Marco Mattavelli, Endri Bezati, Nicolas Zufferey, Malgorzata Maria Michalska

The implementations of signal processing systems on the emerging many-core or multi-core processing platforms require to solve a very difficult problem: how to partition and schedule the processing tasks according to given optimization functions such as da ...

2016

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Zero ASIC

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Tradeoffs in Low-Power Accelerators Design for Large-Scale Interferometers

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow

Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures

Abstracting Multi-Core Topologies with MCTOP

Analysis of CMS noise reduction for 65 nm CIS

High-Precision Performance Estimation of Dynamic Dataflow Programs, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

Graph Chatbot

Chat with Graph Search

Analysis of CMS noise reduction for 65 nm CIS

Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Tradeoffs in Low-Power Accelerators Design for Large-Scale Interferometers

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow

High-Precision Performance Estimation of Dynamic Dataflow Programs, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

Abstracting Multi-Core Topologies with MCTOP