Phase-locked loop

Summary

A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. There are several different types; the simplest is an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop. The oscillator's frequency and phase are controlled proportionally by an applied voltage, hence the term voltage-controlled oscillator (VCO). The oscillator generates a periodic signal of a specific frequency, and the phase detector compares the phase of that signal with the phase of the input periodic signal, to adjust the oscillator to keep the phases matched. Keeping the input and output phase in lockstep also implies keeping the input and output frequencies the same. Consequently, in addition to synchronizing signals, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. These properties are used for

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It has already been a few years since the first appearance of micro-electromechanical systems (MEMS) in academic research. Since then, a broad number of devices have been designed under this generic term. Bulk-acoustic wave (BAW) resonators are among the few of them which have become exploited at industrial level. They are mainly used to implement filters for mainstream telecommunication applications. In a different domain, potential applications for integrated wireless transceivers are flourishing. While some of them require always higher data rates, others need devices with low data rate but even lower power consumption. The goal of this thesis is to explore ways of using BAW resonators to implement building blocks for such a low-power radio and actually verify the postulate that this could help improving power consumption as well as miniaturize key functionalities. For the active integrated circuit part, the choice of a standard digital 0.18µm CMOS process established itself for its low cost and ubiquity. The specifications for the developed radio receiver are calculated for a physical layer derived from the well known Bluetooth communication protocol in the 2.4GHz ISM band with similar applications scenarii but with much lower data rates and wider channel spacing. After presenting the advantages and limitations of the devices, the implications for using BAWresonators to implement a low-power radio are investigated at circuit and system levels and a super-heterodyne architecture is proposed. A selective low-noise amplifier (LNA) is used at the circuit front-end to yield image and blocker rejection. Measurements for the RF front-end comprising an external balun, the selective LNA, a first downconversionmixer and an intermediate-frequency (IF) amplifier showed an overall noise figure of 11dB for a current consumption of 1.5mA under 1.2V. The high selectivity of the design yields an image rejection ratio of at least 50dB and allows to decrease linearity requirements and thus power consumption. A slightly improved version of the same front-end integrated together with the analog baseband signal processing chain but still using external local oscillators showed sensitivities of -96dBm at 100kbps symbol rate and -93dBm at 200kbps with an external state-of-the art FSK demodulator, allowing to extrapolate a global noise figure of 12.2dB for a global current consumption of 2.3mA under 1.2V. The proposed solution for the frequency synthesis uses both a BAW oscillator for the first downconversion to IF and a quadrature quasi-harmonic relaxation oscillator to translate the signals to baseband. The relaxation oscillator is embedded within a phase-locked loop (PLL) for which all the required blocks are discussed. Particularly, a novel modular multi-modulus frequency divider is presented, which does not necessitate complicated logic to yield the wanted division ratio and uses dynamic logic. The necessary digital circuitry to control the frequency generation is discussed as well. Finally, measurements for the complete receiver using the proposed frequency synthesis as well as digital control and demodulator implemented on FPGA are presented.

EPFL2008

Focused electron- and ion-beam induced processing are well established techniques for local deposition and etching that rely on decomposition of precursor molecules by irradiation. These high-resolution nanostructuring techniques have various applications in nanoscience including attach-and-release procedures in nanomanipulation and fabrication of sensors (magnetic, optical and thermal) for scanning probe microscopy. However, a complete physical and chemical understanding of the process is hampered by the lack of suitable means to monitor and to access the numerous interrelated and time-varying process parameters (deposition and etch rate, yield, molecule flux and adsorption/desorption). This thesis is a first attempt to fill this gap. It is based on experimental and simulative approaches for the determination of process conditions and mechanical properties of deposited materials: Mass and force sensors: The use of tools merging micromechanical cantilever sensors and scanning electron microscopy was demonstrated for in situ monitoring and analysis. A cantilever-based resonant mass sensing setup was developed and used for real-time mass measurements. A noise level at the femtogram-scale was achieved by tracking the resonance frequency of a temperature stabilized piezoresistive cantilever using phase-locking. With this technique the surface coverage and residence time of (CH3)3PtCpCH3 molecules, the mass deposition rate, the yield, and the material density of corresponding deposits were measured. In situ cantilever-based static force sensing and mechanical modal vibration analysis were employed to investigate the Young's modulus and density of individual high aspect ratio deposits from the precursor Cu(hfac)2. Precursor supply simulations and experiments: A prerequisite to understand and quantify irradiative precursor chemistry is the knowledge of the local flux of molecules impinging on the substrate. Therefore, Monte Carlo simulations of flux distributions were developed and gas flows injected into a vacuum chamber were analyzed experimentally for the precursors Co2(CO)8, (hfac)CuVTMS, and [(PF3)2RhCl]2. The process parameters extracted from the mentioned approaches are valuable input for numerical focused electron- and ion-beam induced process models (Monte Carlo, continuum). We evaluated the precursor surface diffusion coefficient and the electron impact dissociation cross-section by relating deposit shapes to a continuum model.

EPFL2008

The aim of this thesis is to implement, analyze and improve the selected low noise clock generation and distribution techniques for ADC implementations. The thesis is divided into two parts. The first part focuses on the sampling phase generation and distribution from a low noise clock source. The development and the implementation of the low noise sampling clock phase generation system for a 16-channel TI-SAR ADC while taking advantage of 28nm FDSOI technology is presented. A delay-locked-loop (DLL) is used for this purpose with a 750MHz input frequency. To change the delay, the body-bias technique of the FDSOI technology is utilized so that the number of noise contributors within the delay line is reduced. To use body- biases of both the PMOS and NMOS transistors, a dual-control mechanism which consists of coarse and fine controls has been developed. Moreover, to increase the range of the delay generated by the delay line, a range extender circuit which drives only one charge pump input is developed. This also reduces the charge pump noise added to the system. There are two tape-outs done for the DLL. The first tape-out includes only a delay line and compares simulation results with the measurement for the delay generated. The results show that the simulations and the measurements are consistent. The second tape-out includes the DLL with the 16-channel TI-SAR ADC. The DLL measurements show that the delay range is almost doubled and around ±11%. However, the noise generated within the loop can not be observed with the measurement setup, and it is believed that it is buried under the noise coming from other sources. Secondly, The detailed analysis and the modeling of sub-sampling phase-locked-loop (SSPLL) is done. The aim is to find the limits of its capture range, and to improve the stability margins. The stability limits are also established mathematically. The SSPLL modeling is done in discrete time domain, which allows fast simulations in MATLAB. The capture range is analyzed for different aspects and simulated in MATLAB. Firstly, the linear range extension of the phase detector is examined for both the first and the second order loops. It is shown that the first order loop extends the capture range as the linear range is extended due to the reduction in the phase detector gain. Secondly, sub-sampling phase detector (SSPD) with master-slave switch implementation is examined in discrete time domain for timing nonidealities. The MATLAB simulations also show that the phase margin decreases significantly with large capture ranges, and it is shown that adding a secondary path which delays the sampled voltage one clock cycle increases the phase margin. The last part of the thesis focuses on the circuit implementation of SSPLL with increased phase margin in 28nm FDSOI technology. The aim is to understand how much the lock range is affected when implemented with the transistor level circuit elements. Moreover, the major nonlinearity sources of the SSPLL are investigated. It is observed that the main nonlinearity source is the VCO. It is seen that the capture ranges of both SSPD versions are around ±0.3 of the reference frequency, which is close to the one given by the MATLAB simulations.

EPFL2021