Concept

Resistor–transistor logic

Related publications (84)

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Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic blocks of FPGAs for fast addition. Conventional intuition is that such carry c ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Influence of Information Leakage in Analog Memory on Learning Kohonen Network on Silicon

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The paper presents an influence of leakage effect observed in capacitive analog memories on learning process in hardware implemented Kohonen neural networks with MOS transistors used as switches connected with information holding capacitors. The learning r ...

Ieee Service Center2009

A VHDL-AMS Modeling Methodology for Top-Down/Bottom-Up Design of RF Systems

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This paper presents a modelling methodology for the top-down/bottom-up design of RF systems based on systematic use of VHDL-AMS models. The model interfaces are parameterizable and pin-accurate. The designer can choose to parameterize the models using perf ...

ECSI2009

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The paper deals with the oscillator applications based on vibrating mode of the suspended gate SG-MOSFET transistor. In order to simulate the electrical behavior of the transistor a small-signal equivalent circuit of the gate is proposed and validated. An ...

2008

Barrier-layer scaling of InAlN/GaN HEMTs

Nicolas Grandjean, Jean-François Carlin, Eric Feltin, Marcel Py, Marcus Gonschorek

We discuss the characteristics of In0.17Al0.83N/GaN high-electron mobility transistors with barrier thicknesses between 33 and 3 nm, which are grown on sapphire substrates by metal-organic chemical vapor deposition. The maximum drain current (at V-G = +2.0 ...

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Prospects for logic-on-a-wire

Giovanni De Micheli, Mihai Adrian Ionescu, David Atienza Alonso, Didier Bouvet, Kirsten Emilie Moselund, Yusuf Leblebici, Mohamed Haykel Ben Jamaa

In this paper we present the top-down fabrication of gate-all-around (GAA) and body-tied @W-gate devices by a combination of etching and oxidation steps resulting in a local silicon-on-insulator structure. The GAA has advantages in terms of enhanced curren ...

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Fluoride plasma treatment similar to that used in AlGaN/GaN HEMTs has been applied to InAlN/GaN HEMTs. Enhancement mode of operation is obtained with a pinch-off voltage shifted by 3 V. Owing to the fluoride treatment an increase of the forward gate thresh ...

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Low Overhead DFT Using CDFG by Modifying Controller

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A novel design-for-test (DFT) method that requires minor modifications to the controller in the register-transfer level (RTL) description of a circuit is presented. The control/data flow graph representation of an RTL circuit is used for analysing the test ...

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This paper presents the design flow from system-level specifications to transistor-level design for three different fully-differential amplifiers composing the first and the second integrator of a second-order hybrid multi-bit ΔΣ modulator. The circuit-lev ...

2007

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