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We demonstrate a program-erasable metal-insulator-silicon capacitor with a dielectric structure of SiO2/HfO2-Al2O3 nanolaminate (HAN)/Al2O3. The memory capacitor exhibits a high capacitance density of 4.5 fF/mu m(2), a large memory window of 1.45 V in the ...
This paper describes the architecture of eNVy, a large non-volatile main memory storage system built primarily with Flash memory. eNVy presents its storage space as a linear, memory mapped array rather than as an emulated disk in order to provide an effici ...
The CERN Host Interface (CHI) is a family of interfaces to interconnect Fastbus, VMEbus, and external host computers. The Fastbus interface consists of a processor board (CHI-P) and host-specific I/O ports allowing connection using fast parallel or serial ...
To perform a current sensing in capacitorless 1-transistor (IT) DRAMs on SOI, we have developed a sensing scheme with automatic reference generation. The reference current is generated by an adjustable current source. The electrical calibration of the refe ...
This brief presents a fully integrated nanoelectromechanical system (NEMS) resonator, operable at frequencies in the megahertz range, together with a compact built-in CMOS interfacing circuitry. The proposed low-power second-generation current conveyor cir ...
Non volatile flash memories based on nanoparticles are one of the possible routes to further downscaling of CMOS technology. The increase of scale integration should involve some new features for memory cells such as Coulomb blockade and quantized charging ...
