Publications related to Memory access pattern

Determining an optimum quantity of interleaved instruction streams of defined coroutines

Anastasia Ailamaki, Georgios Psaropoulos

A method for optimizing memory access for database operations is provided. The method may include performing a first database operation by at least executing a first instruction stream associated with the first database operation. The first database opera ...

2023

WR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

David Atienza Alonso, Miguel Peon Quiros, Benoît Walter Denkinger

Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implementing a particular functionality for a given set of constraints. However, the ...

2022

Inter-actions parallel execution on GPU from high-level dataflow synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Recent GPU architectures make available numbers of parallel processing units that exceed by orders of magnitude the ones offered by CPU architectures. Whereas programs written using dataflow programming languages are well suited for programming heterogeneo ...

IEEE2022

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Andreas Peter Burg, Reza Ghanaatian Jahromi

A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomi ...

2022

Manycore clique enumeration with fast set intersections

Paolo Ienne, Kubilay Atasu, Radu Ioan Stoica, Jovan Blanusa

Listing all maximal cliques of a given graph has important applications in the analysis of social and biological networks. Parallelisation of maximal clique enumeration (MCE) algorithms on modern manycore processors is challenging due to the task-level par ...

ACM2020

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Babak Falsafi, Javier Picorel Obando, Abhishek Bhattacharjee

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TL ...

2020

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon

Hybrid caches consisting of both SRAM and emerging Non-Volatile Random Access Memory (eNVRAM) bitcells increase cache capacity and reduce power consumption by taking advantage of eNVRAM's small area footprint and low leakage energy. However, they also inhe ...

2020

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Shabnam Sheikhha

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches) a ...

ASSOC COMPUTING MACHINERY2020

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Memory access pattern

Determining an optimum quantity of interleaved instruction streams of defined coroutines

WR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

Inter-actions parallel execution on GPU from high-level dataflow synthesis

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

High-Level Synthesis of Dynamically Scheduled Circuits

Manycore clique enumeration with fast set intersections

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Graph Chatbot

Chat with Graph Search

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Inter-actions parallel execution on GPU from high-level dataflow synthesis

WR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

High-Level Synthesis of Dynamically Scheduled Circuits

Determining an optimum quantity of interleaved instruction streams of defined coroutines

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Manycore clique enumeration with fast set intersections