Publications related to Intel 8051

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Efficient large-scale graph processing is crucial to many disciplines. Yet, while graph algorithms naturally expose massive parallelism opportunities, their performance is limited by the memory system because of irregular memory accesses. State-of-the-art ...

IEEE COMPUTER SOC2021

Distributed Logless Atomic Durability with Persistent Memory

Babak Falsafi, Alexandros Daglis, Siddharth Gupta

Datacenter operators have started deploying Persistent Memory (PM), leveraging its combination of fast access and persistence for significant performance gains. A key challenge for PM-aware software is to maintain high performance while achieving atomic du ...

2019

A Sensor Network Architecture for Digital SiPM-Based PET Systems

Edoardo Charbon, Claudio Bruschini, Francesco Gramuglia

Digital silicon photo-multipliers (SiPMs) have emerged in the recent past as a viable low cost alternative to photomultiplier tubes in positron emission tomography systems, providing multiple timestamps, energy and scintillation coordinates at high spatial ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

Methods and systems for skew tolerance in and advanced detectors for vector signaling codes for chip-to-chip communication

Mohammad Amin Shokrollahi, Anant Pratap Singh

Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicat ...

2016

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

Davide Sacchetto, Yusuf Leblebici, Tugba Demirci

A non-volatile latch circuitry, comprising a Re RAM cell configured to store a final value of the non-volatile latch circuitry; a data selection circuitry configured to connect or disconnect a data input to a plus voltage node and a minus voltage node of t ...

2014

System design of a 24 GHz phased-array front-end for low-power applications

Pierre-André Farine, Cyril Botteron, Gabriele Tasselli, Ban Wang

This paper deals with the design of a 4-channel phased-array receiver Front-End (FE) architecture working at 24 GHz. Targeting low power applications such as radar sensors and medium bit-rate transceivers, a local oscillator shifting architecture is propos ...

2012

Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands

Yusuf Onur Koçberber, Ilknur Cansu Kaynak

In contemporary superscalar microprocessors, issue queue is a considerable energy dissipating component due its complex scheduling logic. In addition to the energy dissipated for scheduling activities, read and write lines of the issue queue entries are al ...

2010

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Intel 8051

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Distributed Logless Atomic Durability with Persistent Memory

A Sensor Network Architecture for Digital SiPM-Based PET Systems

Methods and systems for skew tolerance in and advanced detectors for vector signaling codes for chip-to-chip communication

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

Power-Efficient Pipelined Analog-to-Digital Converter Architectures for Advanced CMOS Technologies

System design of a 24 GHz phased-array front-end for low-power applications

Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands

Speculative sequential consistency with little custom storage

Graph Chatbot

Chat with Graph Search

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Distributed Logless Atomic Durability with Persistent Memory

A Sensor Network Architecture for Digital SiPM-Based PET Systems

Methods and systems for skew tolerance in and advanced detectors for vector signaling codes for chip-to-chip communication

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

Power-Efficient Pipelined Analog-to-Digital Converter Architectures for Advanced CMOS Technologies

System design of a 24 GHz phased-array front-end for low-power applications

Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands

Speculative sequential consistency with little custom storage