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A Pixel Design of a Branching Ultra-Highspeed Image Sensor

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

BLADE: A BitLine Accelerator for Devices on the Edge

HetExchange: Encapsulating heterogeneous CPU-GPU parallelism in JIT compiled engines

MAMUT: Multi-Agent Reinforcement Learning for Efficient Real-Time Multi-User Video Transcoding

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache