Concept
Zen 3
Publications associées (16)
A Pixel Design of a Branching Ultra-Highspeed Image Sensor
A burst image sensor named Hanabi, meaning fireworks in Japanese, includes a branching CCD and multiple CMOS readout circuits. The sensor is backside-illuminated with a light/charge guide pipe to minimize the temporal resolution by suppressing the horizont ...
2021HetExchange: Encapsulating heterogeneous CPU-GPU parallelism in JIT compiled engines
Anastasia Ailamaki, Periklis Chrysogelos, Manolis Karpathiotakis, Raja Appuswamy
Modern server hardware is increasingly heterogeneous as hardware accelerators, such as GPUs, are used together with multicore CPUs to meet the computational demands of modern data analytics workloads. Unfortunately, query parallelization techniques used by ...
2019Circuit Design, Architecture and CAD for RRAM-based FPGAs
Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...
EPFL2017Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme
Yusuf Leblebici, Gain Kim, Kiarash Gharibdoust, Chen Cao, Thierry Barailler
This paper presents the design and analysis of a serial link transceiver (TRX) architecture employing analog multi-tone (AMT) signaling for chip-to-chip communication. Multi-tone single-sideband (SSB) signaling scheme is proposed in TRX architecture in ord ...
Ieee-Inst Electrical Electronics Engineers Inc2017A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache
Giovanni De Micheli, Luca Benini
The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-c ...
IEEE2016Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory
Giovanni De Micheli, Luca Benini
3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and l ...
Institute of Electrical and Electronics Engineers2015Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache
Giovanni De Micheli, Siang-Yun Lee
The advent of 3-D fabrication technology makes it possible to stack a large amount of last-level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus, increases system performance. However, the higher power density (i.e., power d ...
2014