Concept

Programmable logic device

Related publications (278)

Performance Optimization and FPGA Implementation of Real-Time Tone Mapping

Yusuf Leblebici, Vladan Popovic, Eliéva Arlette Pignat

This brief analyzes the performance of the hardware-based tone mapping operators for compression of high dynamic range images. The bottlenecks of a tone mapping system are determined and a high-performance field programmable gate array (FPGA) implementatio ...

Institute of Electrical and Electronics Engineers2014

Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

Montserrat Fernandez-Bolanos Badia, Antonios Bazigos, Daniel Grogg

Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring os ...

2014

Pipelined Numerical Integration on Reduced Accuracy Architectures for Power System Transient Simulations

Maher Kayal, Georgios Lilis, Theodoros Kyriakidis, Guillaume Olivier Lanz

This work concerns a dedicated mixed-signal power system dynamic simulator. The equations that describe the behavior of a power system can be decoupled in a large linear system that is handled by the analog part of the hardware, and a set of differential e ...

IEEE2014

Nanowire systems: technology and design (invited paper)

Giovanni De Micheli, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Shashi Kanth Bobba, Michele De Marchi

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

Royal Soc2014

Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies

Adam Shmuel Teman

SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of SR ...

IEEE2014

Compact Modeling of Homojunction Tunnel FETs

Mihai Adrian Ionescu, Wladyslaw Grabinski, Antonios Bazigos, Luca De Michielis, Cem Alper, Arnab Biswas, Nilay Dagtekin

Aggressive scaling of the supply voltage reduces the energy needed for switching of standard CMOS devices. However, advanced CMOS technologies are facing two main problems that consequently lead to higher power consumption: the complexity of a further supp ...

IEEE2014

Alignment of the CMS tracker with LHC and cosmic ray data

Jian Wang, Matthias Finger, Lesya Shchutska, Qian Wang, Matthias Wolf, Varun Sharma, Konstantin Androsov, Jan Steggemann, Roberto Castello, Alessandro Degano, Mingkui Wang, João Miguel das Neves Duarte, Lei Zhang, Tian Cheng, Yixing Chen, Werner Lustermann, Andromachi Tsirou, Alexis Kalogeropoulos, Andrea Rizzi, Ioannis Papadopoulos, Paolo Ronchese, Thomas Muller, Giuseppe Codispoti, Paul Turner, Wei Sun, Raffaele Tito D'Agnolo, Jie Chen, Davide Ceresa, Ji Hyun Kim, Donghyun Kim, Dipanwita Dutta, Zheng Wang, Sanjeev Kumar, Wei Li, Yong Yang, Ajay Kumar, Ashish Sharma, Georgios Anagnostou, Joao Varela, Csaba Hajdu, Muhammad Ahmad, Ekaterina Kuznetsova, Ioannis Evangelou, Matthias Weber, Muhammad Shoaib, Vineet Kumar, Vladimir Petrov, Francesco Fiori, Quentin Python, Meng Xiao, Hao Liu, Sourav Sen, Marco Trovato, Gurpreet Singh, Xiao Wang, Kai Yi, Rajat Gupta, Shuai Liu, Aram Avetisyan, Yu Zheng, Charles Dietz, Michal Simon, Matteo Marone, Giovanni Bianchi, Wenjing Wu, Yifei Guo, Yu Fu, Stefano Michelis, Federico Faccio, Stéphane Détraz

The central component of the CMS detector is the largest silicon tracker ever built. The precise alignment of this complex device is a formidable challenge, and only achievable with a significant extension of the technologies routinely used for tracking de ...

2014

TSPC Flip-Flop Circuit Design with Three-Independent-Gate Silicon Nanowire FETs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Jian Zhang

True Single-Phase Clock (TSPC) Flip-Flops, based on dynamic logic implementation, are area-saving and high-speed compared to standard static flip-flops. Furthermore, logic gates can be embedded into TSPC flip-flops which significantly improves performance. ...

IEEE2014

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Georgios Karakonstantis

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped p ...

Elsevier2014

Perovskite as Light Harvester: A Game Changer in Photovoltaics

Michael Graetzel, Mohammad Khaja Nazeeruddin

It is not often that the scientific community is blessed with a material, which brings enormous hopes and receives special attention. When it does, it expands at a rapid pace and its every dimension creates curiosity. One such material is perovskite, which ...

Wiley-Blackwell2014

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