Publications related to Cell (processor)

Compact low-power recording architecture for multichannel acquisition of biological signals and method for compressing said biological signal data

Alexandre Schmid, Mahsa Shoaran, Mahdad Hosseini Kamal

The present invention relates to a method for compressing signal data of a plurality of biological signals captured by a plurality of implanted measurement devices. The present invention further relates to an implantable sensor configured to carry out said ...

2016

Characterization of intralaminar mode I fracture of AS4/PPS composite using inverse identification and micromechanics

John Botsis, Georgios Pappas, Luis Pablo Canal Casado

A detailed experimental-numerical study of large scale bridging during intralaminar fracture of AS4/PPS uniaxial thermoplastic composite is reported. Identification of bridging tractions is carried out using: (a) An inverse identification method based on q ...

Elsevier2016

Real-Time Probabilistic Heart Beat Classification and Correction for Embedded Systems

David Atienza Alonso, Francisco Javier Rincon Vallejos, Srinivasan Murali, Grégoire Casimir Joseph Surrel

With the emergence of wearable and non-intrusive med- ical devices, one major challenge is the real-time analysis of the acquired signals in real-life and ambulatory con- ditions. This paper presents a lightweight algorithm for on-line heart beat classific ...

2015

Whole cell screen based identification of spiropiperidines with potent antitubercular properties

Stewart Cole, Ruben Hartkoorn

Whole cell based screens to identify hits against Mycobacterium tuberculosis (Mtb), carried out under replicating and non-replicating (NRP) conditions, resulted in the identification of multiple, novel but structurally related spiropiperidines with potent ...

Elsevier2015

A Case for Specialized Processors for Scale-Out Workloads

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman, Mohammad Alisafaee, Yusuf Onur Koçberber, Stavros Volos, Ilknur Cansu Kaynak, Adrian Daniel Popescu, Al Mutaz Adileh

Emerging scale-out workloads need extensive amounts of computational resources. However, datacenters using modern server hardware face physical constraints in space and power, limiting further expansion and requiring improvements in the computational densi ...

Ieee Computer Soc2014

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

Marco Mattavelli, Endri Bezati, Ghislain Roquier, Richard Thavot

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has move ...

Springer Heidelberg2014

Cyme: A Library Maximizing SIMD Computation on User-Defined Containers

Felix Schürmann, Timothée Ewart

This paper presents Cyme, a C++ library aiming at abstracting the usage of SIMD instructions while maximizing the usage of the underlying hardware. Unlike similar efforts such as Boost.simd or VC, Cyme provides generic high level containers to the users wh ...

Springer International Publishing2014

Approximate Compressed Sensing: Ultra-Low Power Biosignal Processing via Aggressive Voltage Scaling on a Hybrid Memory Multi-core Processor

David Atienza Alonso, Pierre Vandergheynst, Luca Benini, Hossein Mamaghanian

Technology scaling enables the design of low cost biosignal processing chips suited for emerging wireless body-area sensing applications. Energy consumption severely limits such applications and memories are becoming the energy bottleneck to achieve ultra- ...

IEEE/ACM Press2014

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Samuel Burri, Philip Brisk

Instruction set extensions (ISEs) improve the performance and energy consumption of application-specific processors. ISEs can use architecturally visible storage (AVS), localized compiler-controlled memories, to provide higher I/O bandwidth than reading da ...

Assoc Computing Machinery2014

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Cell (processor)

Compact low-power recording architecture for multichannel acquisition of biological signals and method for compressing said biological signal data

Characterization of intralaminar mode I fracture of AS4/PPS composite using inverse identification and micromechanics

Memory Systems and Interconnects for Scale-Out Servers

Real-Time Probabilistic Heart Beat Classification and Correction for Embedded Systems

Whole cell screen based identification of spiropiperidines with potent antitubercular properties

A Case for Specialized Processors for Scale-Out Workloads

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

Cyme: A Library Maximizing SIMD Computation on User-Defined Containers

Approximate Compressed Sensing: Ultra-Low Power Biosignal Processing via Aggressive Voltage Scaling on a Hybrid Memory Multi-core Processor

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Graph Chatbot

Chat with Graph Search

Real-Time Probabilistic Heart Beat Classification and Correction for Embedded Systems

Memory Systems and Interconnects for Scale-Out Servers

Characterization of intralaminar mode I fracture of AS4/PPS composite using inverse identification and micromechanics

Compact low-power recording architecture for multichannel acquisition of biological signals and method for compressing said biological signal data

Whole cell screen based identification of spiropiperidines with potent antitubercular properties

A Case for Specialized Processors for Scale-Out Workloads

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

Cyme: A Library Maximizing SIMD Computation on User-Defined Containers

Approximate Compressed Sensing: Ultra-Low Power Biosignal Processing via Aggressive Voltage Scaling on a Hybrid Memory Multi-core Processor

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage