Lecture
This lecture discusses the historical evolution of memory cells per chip, following Moore's Law, and the increasing importance of memory in semiconductor markets. It covers the architecture of SRAM and DRAM, memory testing techniques, fault models like SAF, TF, DRF, CF, and NPSF, and March tests concepts. The instructor explains the GALPAT and walking 1/0 tests, linked faults, and masking in memory testing.