Lecture

Logic Gates and IC Technology

Description

This lecture covers the implementation of logic gates in semiconductor material, focusing on two main logic families: Transistor to Transistor Logic (TTL) and Complementary Metal Oxide Silicon (CMOS). It discusses the technology of Integrated Circuits (ICs), static and dynamic hazards, gated clocks, real D flip-flops, metastability, critical path, maximum clock frequency, and switch debouncing. The lecture also delves into the elimination of static hazards using Karnaugh maps, the theory of zero-delay models, and the construction of NOR gates in TTL and CMOS technologies.

About this result
This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.