Path-Delay Fault Testing

This lecture covers the concept of linked and unlinked faults in VLSI systems, where linked faults may mask each other, affecting test results. It also explains various March test algorithms for detecting faults, including MATS+, MARCH C-, and MARCH A. The importance of irredundant tests and the complexity of delay testing for asynchronous circuits are discussed. The lecture delves into circuit delays, critical paths, and the detection of path-delay faults, emphasizing the need for robust test generation to ensure fault detection. Additionally, the lecture introduces the concept of non-robust and robust path-delay tests, highlighting the efficient representation of transitions using a five-valued algebra for path-delay tests.

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Logic family

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