Path-Delay Fault Testing

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Logic Systems: TTL Gates and Analog Aspects

Explores TTL gates, analog aspects, and various logic gates in digital circuits.

Logic Systems: Karnaugh Maps and TTL Gates

Explores Karnaugh maps, TTL gates, analog aspects of digital logic, and prime implicants.

Karnaugh Maps: Grouping Techniques

Explores Karnaugh maps, grouping rules, and transistor logic in logic systems.

Digital Systems Overview: Evolution and Fundamentals

Explores the evolution of digital systems, covering basics like Boolean algebra and logic gates, and emphasizes teamwork skills and professional vocabulary.

Static Logic Fundamentals

Covers the fundamentals of static logic, including noise immunity, noise margins, and various logic gate designs.

Logic Gates and IC Technology

Explores the implementation of logic gates in semiconductor material, focusing on TTL and CMOS technologies, ICs, hazards, clocks, D flip-flops, and switch debouncing.

Test of VLSI Systems: Combinational and Sequential ATPG

Covers the generation of test vector patterns, fault modeling, structural vs. functional tests, and the implementation of time-frame expansion.

Testing of VLSI Systems

Explores defects, errors, and fault models in VLSI systems, emphasizing fault collapsing and dominance.

Complex CMOS Logic Gates

Explores the construction, delay, and sizing of CMOS logic gates, including strategies for transistor sizing and dealing with fan-in.

Logic Synthesis: Designing Efficient Digital Circuits

Discusses logic synthesis techniques for designing efficient digital circuits using minterms, maxterms, and new gates like XOR and XNOR.