Lectures related to Path-Delay Fault Testing

Introduces Logisim Evolution, focusing on basic components for digital circuit design.

Covers solutions for creating logic gates using neural networks and introduces the XOR gate and Recurrent Neural Networks (RNN).

Explores dynamic logic fundamentals, hazards, charge-sharing issues, clocking schemes, and various implementations to enhance performance.

Discusses digital logic circuits, focusing on CMOS technology and Verilog modeling techniques.

Delves into the fundamental limits of power dissipation in computing and explores emerging concepts using 2D materials.

Covers the Logical Effort method for optimizing logic delay and gate sizing impact.