Semicustom RTL Design: Frontend with Synthesis

Related lectures (31)

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Covers pulse generation, edge detection, common design mistakes, and clock/reset signals in logic circuits.

Covers the basic principles and architecture of Field Programmable Gate Arrays (FPGAs) and their implementation options for digital circuits.

Explores the impact of PVT variations, uncertainties in IC design, worst-case design paradigms, and the importance of Monte-Carlo simulations.

Covers basic VHDL constructs for RTL design, including arithmetic, multiplexers, registers, and instantiation.

Discusses digital logic circuits, CMOS technology, and Verilog for circuit design.

Explores challenges in hardware verification, clear specifications, speculation harm, and cycle-precise semantics.

Covers the setup and access to virtual machines for IC design practical exercises.

Introduces the basics of physical design in VLSI chip design, emphasizing layout features, power supply wiring, and gate layout optimization.

Focuses on implementing a square function generator using Speedgoat FPGA technology and real-time signal processing techniques.

Presents the development of a verified high-level synthesis compiler for elastic circuits.