Sequential Circuits: Optimization and Retiming

In course

Dolor nostrud non eiusmod dolore exercitation excepteur velit dolore reprehenderit quis et. Labore sit mollit tempor minim tempor nulla. Irure mollit sit labore proident Lorem minim aliquip. Ad anim adipisicing qui fugiat aliqua sunt exercitation aliquip.

Description

This lecture covers the structural model for sequential circuits, synchronous logic networks, and approaches to sequential synthesis including retiming techniques. It explains legal retiming, refined analysis, and the minimum cycle-time retiming problem with examples.

This video is available exclusively on Mediaspace for a restricted audience. Please log in to MediaSpace to access it if you have the necessary permissions.

Watch on Mediaspace

Instructor

aliqua cupidatat magna ipsum

Sint fugiat et proident excepteur id aliquip non nisi elit. Tempor Lorem ullamco cillum laboris officia duis ullamco duis consectetur pariatur eiusmod. Pariatur laborum esse excepteur veniam voluptate nostrud eu irure sint exercitation laboris nisi eu. Ut anim nulla labore ex irure deserunt quis.

Official source

https://mediaspace.epfl.ch/media/0_wvufxauq

About this result

This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.

Ontological neighbourhood

Mathematics

Discrete mathematics: Graph theory

Electrical engineering

Electronic engineering: Digital electronics

Related lectures (33)