Sequential Circuits: Optimization and Retiming

In course

Voluptate laborum reprehenderit cillum do id sit non. Culpa quis non velit amet laboris nulla pariatur nostrud qui. Dolor nulla pariatur eiusmod occaecat veniam ullamco laboris Lorem mollit occaecat laboris. Dolor ea sit tempor magna officia id et in proident qui in ut cupidatat. Officia mollit tempor nisi magna consectetur ex id sunt. Aute occaecat in consequat non culpa nostrud cillum magna.

Description

This lecture covers the structural model for sequential circuits, synchronous logic networks, and approaches to sequential synthesis including retiming techniques. It explains legal retiming, refined analysis, and the minimum cycle-time retiming problem with examples.

This video is available exclusively on Mediaspace for a restricted audience. Please log in to MediaSpace to access it if you have the necessary permissions.

Watch on Mediaspace

Instructor

consequat Lorem

Velit sint sunt anim excepteur dolor commodo. Consectetur elit exercitation officia ipsum et proident eu irure sit dolore aute. Culpa ad eiusmod eiusmod tempor incididunt ullamco mollit consectetur ex deserunt proident non duis Lorem. Consectetur ex eu ullamco anim deserunt dolore mollit consectetur officia eu laboris eu enim. Veniam irure excepteur ullamco aute dolor tempor id sunt labore commodo est labore eu occaecat. Est mollit qui ipsum culpa fugiat eu mollit eu ut labore commodo consequat. Eiusmod sit eiusmod eiusmod cupidatat pariatur quis.

Official source

https://mediaspace.epfl.ch/media/0_wvufxauq

About this result

This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.

Ontological neighbourhood

Mathematics

Discrete mathematics: Graph theory

Electrical engineering

Electronic engineering: Digital electronics

Related lectures (33)