Keylock in VHDL and on FPGACovers the design of a KeyLock system in VHDL, focusing on the FSM implementation for key validation and LED indication.
Universal Source CodingCovers the Lempel-Ziv universal coding algorithm and invertible finite state machines in information theory.
Finite State Machine (Door Lock)Covers the design of a Finite State Machine for a door lock system and explains the Moore FSM model with key validation and LED indicators.
Formally Verified Chisel DesignsExplores formally verifying Chisel designs using SMT solvers and covers examples like delayed assertions and proofs by induction.