Publications by Serge Ecoffey | EPFL Graph Search

Ultra-thin nanograin polysilicon devices for hybrid CMOS-NANO integrated circuits

The aim of this research is to develop and to evaluate devices and circuits performances based on ultrathin nanograin polysilicon wire (polySiNW) dedicated to room temperature operated hybrid CMOS-"nano" integrated circuits. The proposed polySiNW device is ...

EPFL2007

Electrical conduction in 10 nm thin polysilicon wires from 4 to 400 K and their operation for hybrid memory

Mihai Adrian Ionescu, Didier Bouvet, Santanu Mahapatra, Serge Ecoffey

2006

Hybrid Nanowire-MOS circuit architectures: from basic physics to digital and analog applications

Mihai Adrian Ionescu, Didier Bouvet, Vincent Pott, Santanu Mahapatra, Serge Ecoffey

2006

Electrical conduction in 10nm-thin polysilicon wires from 4K to 400K and their operation for hybrid memory

Mihai Adrian Ionescu, Didier Bouvet, Serge Ecoffey

2005

Nanowire for Room Temperature Operated Hybrid CMOS-‘NANO’ Integrated Circuits

Mihai Adrian Ionescu, Alexandre Schmid, Michel Declercq, Yusuf Leblebici, Vincent Pott, Marco Mazza, Serge Ecoffey

2005

New Logic Family Based on Hybrid MOSFET-Polysilicon Nano-Wires

Mihai Adrian Ionescu, Alexandre Schmid, Michel Declercq, Didier Bouvet, Yusuf Leblebici, Vincent Pott, Marco Mazza, Serge Ecoffey

2005

Low temperature investigation of electrical conduction in polysilicon: simulation and experiment

Mihai Adrian Ionescu, Didier Bouvet, Vincent Pott, Santanu Mahapatra, Serge Ecoffey

2005

Fabrication of polysilicon gated-nanowires and their application for pA precision current measurements

Mihai Adrian Ionescu, Michel Declercq, Didier Bouvet, Yusuf Leblebici, Vincent Pott, Serge Ecoffey

2005

A hybrid CMOS-SET co-fabrication platform using nano-grain polysilicon wires

Mihai Adrian Ionescu, Didier Bouvet, Vincent Pott, Santanu Mahapatra, Serge Ecoffey

This paper presents a process for the co-fabrication of self-aligned NMOS and single electron transistors made by gated polysilicon wires. The realization of SET–MOS hybrid architectures is also reported. The proposed process exploits an original low energ ...

2005