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Yusuf Leblebici

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Yusuf Leblebici

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A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Column-Separated Compressive Sampling Scheme for Low Power CMOS Image Sensors

High Frame-Rate Low-Power Compressive Sampling CMOS Image Sensor Architecture

A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA

Applications of Multi-Terminal Memristive Devices: A Review

Characterization of Standard CMOS Compatible Photodiodes and Pixels for Lab-on-Chip Devices

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

Surface potential compact model for embedded flash devices oriented to IC memory design

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

An event-detection high dynamic range CMOS image sensor